aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 70

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
calibration cycle is initiated by user via the mode bits in the
ADCMDE[2:0] MMR. 2 types of automatic calibration are
available to the user, namely:
Self (Offset or Gain) Calibration, where the ADC generates its
calibration coefficient based on an internally generated 0V in
the case of Self-Offset calibration and full-scale voltage in the
case of Self-Gain calibration. It should be emphasized that ADC
Self-Calibrations correct for offset and gain errors within the
ADC. Self-calibrations cannot compensate for other external
errors in the system, e.g. Shunt-Resistor tolerance/drift, external
offset voltages etc.
System (Offset or Gain) Calibration, where the ADC generates
its calibration coefficient based on an externally generated zero-
scale voltage in the case of System-Offset calibration and Full-
scale voltage in the case of System-Gain calibration, which are
applied to the external ADC input for the duration of the
calibration cycle.
The duration of an Offset calibration is 1 single conversion
cycle (3/FADC Chop off, 2/FADC Chop on) before returning
the ADC to idle mode. A Gain calibration is a 2-stage process
and subsequently takes twice as long as an offset calibration
cycle. Once a calibration cycle is initiated, any ongoing ADC
conversion is immediately halted, the calibration is carried out
automatically at an ADC update rate programmed into
ADCFLT and the ADC is always returned to idle after any
calibration cycle. It is strongly recommended that ADC
calibration is initiated at as low an ADC update rate as possible
(high SF value in ADCFLT) in order to minimize the impact of
ADC noise during calibration.
NOTE: in self-calibration mode, ADC0GN must first contain
the values for PGA = 1 before a calibration scheme is started
Using the Offset and Gain Calibration
If the Chop bit (ADCFLT[15]) is enabled, then internal ADC
offset errors will be minimized and an Offset calibration may
not be required. If chopping is disabled however, an initial
Offset calibration will be required and may need to be repeated
particularly after a large change in temperature.
A Gain calibration, particularly in the context of the I-ADC
(with internal PGA) may need to be carried out at all relevant
system gain ranges depending on system accuracy
requirements. If it is not possible to apply an external full-scale
current on all gain ranges then it is possible to apply a lower
current, and scale the result produced by the calibration. e.g
Apply a 50% current and then divide the ADC0GN value
produced by 2 and write this value back into ADC0GN. It
should be noted that there is a lower limit to the input signal
that can be applied for a System-Calibration because the
ADC0GN register is only 16-Bit. The input span (difference
between the System Zero-Scale value and System Full-Scale
value) should be greater than 40% of the nominal Full-Scale-
Input range, that is, > 40% of V
REF
/Gain.
Rev. PrE | Page 70 of 150
The on-chip Flash/EE memory can be used to store multiple
calibration coefficients, which can be copied by user code
directly into the relevant calibration registers as appropriate
based on system configuration. In general, the simplest way to
use the calibration registers is to let the ADC calculate the
values required as part of the ADC automatic calibration
modes.
A factory or end-of-line calibration for the I-ADC would be a
2-step procedure:
1. Apply 0A current.
Configure the ADC in the required PGA setting etc. and write
to ADCMDE[2:0] to perform a System Zero-Scale Calibration.
This writes a new offset calibration value into ADC0OF.
2. Apply a Full-Scale current for the selected PGA setting.
Write to ADCMDE to perform a System Full-Scale Calibration.
This writes a new gain calibration value into ADC0GN.
Understanding the Offset and Gain Calibration Registers
The output of the average block in the ADC signal flow
described earlier after the digital filter and before the Offset and
Gain scaling can be considered to be a fractional number with a
span, for a +/- Full-Scale input, of approx +/-0.75. The span is
less than +/-1.0 because there is attenuation in the modulator to
accommodate some over-range capacity on the input signal.
The exact value of the attenuation will vary slightly from part-
to-part, because of manufacturing tolerances.
The Offset Coefficient is read from the ADC0OF calibration
register. This value is a 16-Bit 2's complement number. The
range of this number, in terms of the signal chain, is effectively
+/-1.0. 1 LSB of the ADC0OF register is therefore not the same
as 1LSB of ADC0DAT.
A positive value of ADC0OF indicates that offset is subtracted
from the output of the filter, a negative value is added. The
nominal value of this register is 0x0000, indicating zero offset is
to be removed. The actual offset of the ADC may vary slightly
from part-to-part and at different PGA gains. The offset within
the ADC is minimized if the Chopping mode is active
(ADCFLT[15]=1).
The Gain Coefficient is a unit less scaling factor. The 16-Bit
value in this register is divided by 16384, and then multiplied by
the offset-corrected value. The nominal value of this register
equals 0x5555, which corresponds to a multiplication factor of
1.3333. This scales the nominal +/-0.75 signal to produce a full-
scale output signal of +/-1.0 which is checked for Overflow/
Underflow and converted to Two's Complement or Unipolar
mode as appropriate, before being output to the Data register.
The actual gain, and the required scaling coefficient for zero
gain error, varies slightly from part to part, and at different PGA
settings and in Normal / Low-Power-Mode. The value
Preliminary Technical Data