aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 69

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
In ADC Low Power Mode, the ADC, Sigma-Delta modulator
clock no longer driven at 512kHz but is driven directly from the
on-chip low power (131kHz) oscillator. Subsequently, for the
same ADCFLT configurations in Normal Mode, all filter values
should be scaled by a factor of approximately four. This means
that it is possible to configure the ADC for 1Hz throughput in
Low Power Mode. The filter frequency response for this
configuration is shown below in Figure 25.
Table 37. Common ADCFLT Configurations
ADC Mode
Normal
Normal
Normal
Normal
Normal
Normal
Low Power
Low Power
Low Power
ADC Calibration
As described in detail in the top-level diagrams at the start of
this section, the signal flow through all ADC Channels can be
described in simple terms as:
An Input-voltage is applied through an input buffer (and PGA
in the case of the I-ADC) to the Sigma-Delta Modulator.
The Modulator-output is applied to a programmable Digital
Decimation Filter.
The filter output result is then averaged if chopping is used.
An Offset value (ADCxOF) is subtracted from the result.
This result is scaled by a Gain value (ADCxGN).
Figure 24. Typical Digital Filter Response at FADC=4Hz, (ADCFLT = 0xBF1D)
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
SF
0x1D
0x1F
0x07
0x07
0x03
0x00
0x10
0x10
0x1F
20
FREQUENCY (kHz)
AF
0x3F
0x16
0x00
0x00
0x00
0x00
0x03
0x09
0x3D
40
Other Config
Chop On
Chop On
None
Sinc 3 Modifiy
Running Average
Running Average
Chop On
Chop On
Chop On
60
Rev. PrE | Page 69 of 150
In general, it should be noted that it is possible to program
different values of SF and AF in the ADCFLT register and
achieve the same ADC update rate. In practical terms, the
trade-off with any value of ADCFLT will be frequency response
versus ADC noise. For optimum filter response and ADC noise
when using combinations of SF and AF, a good rule of thumb to
use would be to first choose an SF in the range of 16 – 40 (dec)
or 0x10 to 0x28 and then increase the AF value to achieve the
required ADC through-put. Table 37 shows some common
ADCFLT configurations.
Finally, the result is formatted as
Each ADC has a specific Offset and Gain correction or
Calibration coefficient associated with it that are stored in
MMR based Offset and Gain registers(ADCxOF and
ADCxGN). The offset and gain registers can be used to remove
offsets and gain errors arising within the part as well as System-
level offset and gain errors external to the part.
These registers are configured at power-on with a factory
programmed calibration value. These factory calibration values
will vary from part to part reflecting the manufacturing
variability of internal ADC circuits. However, these registers
can also be overwritten by user code (only if the ADC is in idle
mode) and will be automatically overwritten if an offset or gain
Figure 25. Typical Digital Filter Response at FADC=1Hz, (ADCFLT = 0xBD1F
ADCFLT
0xBF1D
0x961F
0x0007
0x0087
0x4003
0x4000
0x8310
0x8910
0xBD1F
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
- 2’s Complement. / Offset-Binary,
- Rounded to 16 bits
- Clamped to +/-Full-Scale
0
2
4
6
FADC
4Hz
10Hz
1KHz
1KHz
2KHz
8KHz
20Hz
10Hz
1Hz
FREQUENCY (kHz)
8
ADuC7030/ADuC7033
10
12
14
TSETTLE
0.5secs
0.2secs
3msecs
3msec
2msec
0.5ms
100ms
200ms
2sec
16
18
20