aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 74

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
The operating mode, clocking mode and programmable clock
divider are controlled via two MMRs, PLLCON and POWCON,
and the status of the PLL is indicated by PLLSTA. PLLCON
controls the operating mode of the clock system while
POWCON controls the core clock frequency and the power-
down mode. PLLSTA indicates the presence of an oscillator on
the XTAL1 pin, the PLL Lock status, and the PLL Interrupt.
It is recommended that before the ADuC7030/ADuC7033 is
powered down, that the clock source for the PLL is switched to
the Low Power 131kHz oscillator to reduce wake up time. The
Low Power Oscillator is always active.
When the ADuC7030/ADuC7033 wakes up from power down,
the MCU core will begin executing code once the PLL begins
oscillating. This occurs before the PLL has locked to a
frequency of 20.48MHz. To ensure the Flash/EE memory
controller is executing with a valid clock, the controller is
driven with a PLL-Output/8 clock source while the PLL is
locking. Once the PLL locks, the PLL’s output is switched from
the PLL-Output/8 to the locked PLL-Output.
If user code requires an accurate PLL output, user code must
poll the Lock bit (PLLSTA[1]) after wake-up before resuming
normal code execution.
The PLL will be locked within 2ms, if the PLL is clocked from
an active clock source, e.g. Low Power 131kHz oscillator after
waking up.
PLLSTA Register:
Name:
Address:
Default Value:
Access:
Function:
Table 38. PLLSTA MMR Bit Description
Bit
31 to 3
2
1
0
Description
Reserved
XTAL Clock, Read Only
This is a live representation of the current logic level on XTAL1. This allows the user to check to see if an external clock source is
present. If present, this bit will alternate high and low at a frequency of 32.768kHz.
PLL Lock Status Bit, Read Only
Set when the PLL is locked and outputting 20.48MHz.
Clear when the PLL is not locked and outputting a Fcore/8 clock source
PLL Interrupt:
Set if the PLL Lock status bit signal goes low.
Cleared by writing 1 to this bit
PLLSTA
0xFFFF0400
Read Only
This 8-bit register allows user code to monitor the lock state of the PLL and the status of the external crystal.
Rev. PrE | Page 74 of 150
PLLCON is a protected MMR with two 32-bit keys PLLKEY0, a
pre write key, and PLLKEY1, a post write key.
PLLKEY0 = 0x000000AA
PLLKEY1 = 0x00000055
POWCON is a protected MMR with two 32-bit keys
POWKEY0, a pre write key, and POWKEY1, a post write key.
POWKEY0 = 0x00000001
POWKEY1 = 0x000000F4
An example of writing to both MMRs is shown below:
POWKEY0 = 0x01
POWCON = 0x00
POWKEY1 = 0xF4 //POWCON KEY
iA1*iA2
where iA1 and iA2 are defined as longs and are not 0
PLLKEY0 = 0xAA //PLLCON KEY
PLLCON
PLLKEY1 = 0x55
iA1*iA2
access during clock change
= 0x0
Preliminary Technical Data
//POWCON KEY
//Full Power-down
//dummy cycle to clear the pipe line,
//Switch to LP Osc.
//PLLCON KEY
//dummy cycle to prevent Flash/EE