aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 59

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
ADC Filter Register:
Name:
Address:
Default Value:
Access:
Function:
Note:
Table 32. ADCFLT MMR Bit Designations
Bit
15
14
13 - 8
7
6 – 0
Description
Chop enable
Set by user to enable system chopping of all active ADCs. When this bit is set the ADC will have very low offset errors and drift
but the ADC output rate will be reduced by a factor of 3 if AF=0 (see Sinc3 Decimation Factor bits below). If AF > 0, then ADC
output update rate will be the same with chop on or off. When chop is enabled, the settling time is 2 output periods.
Running Average
Set by user to enable a running average by 2 function reducing ADC noise. This function is automatically enabled when
chopping is active. It is an optional feature when chopping is inactive and if enabled (when chopping is inactive) does not
reduce ADC output rate but will increase the settling time by 1 conversion period.
Cleared by user to disable the running average function.
Averaging Factor ( AF )
The value written to these bits is use to implement a programmable 1
reduce ADC noise at the expense of output rate as described in Sinc Decimation Factor bits below.
Sinc3 Modify
Set by user to modify the standard Sinc3 frequency response to increase the filter stopband rejection by 5dBs approx. This is
achieved by inserting a second notch (NOTCH2) at F
response.
Sinc3 Decimation Factor (SF)
The value (SF) written in these bits controls the over sampling (decimation factor) of the Sinc3 filter. The output rate from the
Sinc3 filter is given by
F
Note : this is valid for all SF values <= 125
For SF= 126, F
For SF= 127, F
For information on calculating the F
Notes:
- Due to limitations on the digital filter internal data-path, there are some limitations on the combinations of SF (Sinc3
Decimation Factor) and AF (Averaging Factor) that can be used to generate a required ADC output rate. This restriction limits
the minimum ADC update in Normal Power Mode to 4Hz or 1Hz in Low Power Mode.
- In low power mode and low power-plus mode, the ADC is driven directly by the low power oscillator (131KHz) and not
512KHz. All F
ADC
= ( 512,000 / ( [SF+1] X 64 )) Hz when the CHOP bit (bit#15 above) = 0 and AF=0 (note AF = Averaging Factor)
ADCFLT
0xFFFF0518
0x0007
Read/Write
The ADC Filter MMR is an 16-bit register that controls the speed and resolution of the on-chip ADCs.
If ADCFLT is modified, the Current and Voltage/Temperature ADCs are reset.
ADC
ADC
ADC
calculations should be divided by 4 (approx).
is forced to 60Hz
is forced to 50Hz
ADC
for SF (other than 126 and 127) and AF values please refer to Table 33.
Rev. Pre | Page 59 of 150
NOTCH2
= 1.333 * F
NOTCH
st
order Sinc post filter. The averaging factor can further
where F
NOTCH
is the location of the 1
ADuC7030/ADuC7033
st
notch in the