aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 62

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
Current Channel ADC Data Register:
Name:
Address:
Default Value:
Access:
Function:
Voltage Channel Data Register:
Name:
Address:
Default Value:
Access:
Function:
Temperature Channel ADC Data Register:
Name:
Address:
Default Value:
Access:
Function:
Current Channel ADC Offset Calibration Register:
Name:
Address:
Default Value:
Access:
Function:
ADC0DAT
0xFFFF0520
0x0000
Read Only
This ADC Data MMR holds the 16-bit conversion result from the I-ADC. The ADC will not update this MMR if the
ADC0 Conversion Result READY bit (ADCSTA[0]) is set. A read of this MMR by the MCU clears all asserted READY
flags (ADCSTA[2:0]).
ADC1DAT
0xFFFF0524
0x0000
Read Only
This ADC Data MMR holds the 16-bit Voltage conversion result from the V/T-ADC. The ADC will not update this
MMR if the Voltage Conversion Result READY bit (ADCSTA[1]) is set. If I-ADC is not active, a read of this MMR by
the MCU clears all asserted READY flags (ADCSTA[2:1]).
ADC2DAT
0xFFFF0528
0x0000
Read Only
This ADC Data MMR holds the 16-bit temperature conversion result from the V/T-ADC. The ADC will not update
this MMR if the Temperature Conversion Result READY bit (ADCSTA[2]) is set. If I-and V ADC is not active, a read
of this MMR by the MCU clears all asserted READY flags (ADCSTA[2]). A ready of this MMR will clear ADCSTA[2].
ADC0OF
0xFFFF0530
Part Specific, factory programmed
Read/Write Access
This ADC Offset MMR holds a 16-bit offset calibration coefficient for the I-ADC. The register is configured at power-
on with a factory default value. However, this register will be automatically overwritten if an offset calibration of the I-
ADC is initiated by the user via bits in the ADCMDE MMR. User code can only write to this calibration register if the
ADC is in idle mode. An ADC must be enabled and in idle mode before written to any Offset or Gain Register. The
ADC must be in idle mode for at least 23µs.
Rev. PrE | Page 62 of 150
Preliminary Technical Data