atmega323l ATMEL Corporation, atmega323l Datasheet - Page 129

• Manufacturer Part Number: atmega323l
• Description: Atmega323 8-bit Avr Microcontroller With 32k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Prescaling and
Conversion Timing
1457G–AVR–09/03
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Voltage reference
and input channel selections will not go into effect until ADEN is set. The ADC does not
consume power when ADEN is cleared, so it is recommended to switch off the ADC
before entering power saving sleep modes.
A conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be set to zero by
hardware when the conversion is completed. If a different data channel is selected while
a conversion is in progress, the ADC will finish the current conversion before performing
the channel change.
The ADC generates a 10-bit result, which are presented in the ADC Data Registers,
ADCH and ADCL. By default, the result is presented right adjusted, but can optionally
be presented left adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content
of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access
to Data Registers is blocked. This means that if ADCL has been read, and a conversion
completes before ADCH is read, neither register is updated and the result from the con-
version is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is
re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes.
When ADC access to the Data Registers is prohibited between reading of ADCH and
ADCL, the interrupt will trigger even if the result is lost.
Figure 61. ADC Prescaler
The successive approximation circuitry requires an input clock frequency between
50 kHz and 200 kHz to achieve maximum resolution. If a lower resolution than 10 bits is
required, the input clock frequency to the ADC can be higher than 200 kHz to achieve a
higher sampling rate. See “ADC Characteristics – Preliminary Data” on page 136 for
more details. The ADC module contains a prescaler, which divides the system clock to
an acceptable ADC clock frequency.
The ADPS bits in ADCSR are used to generate a proper ADC clock input frequency
from any XTAL frequency above 100 kHz. The prescaler starts counting from the
moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler
ADEN
ADPS0
ADPS1
ADPS2
CK
Reset
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
ATmega323(L)
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