atmega323l ATMEL Corporation, atmega323l Datasheet - Page 53

• Manufacturer Part Number: atmega323l
• Description: Atmega323 8-bit Avr Microcontroller With 32k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Asynchronous Operation of
Timer/Counter2
1457G–AVR–09/03
If a write is performed to any of the three Timer/Counter2 Registers while its Update
Busy Flag is set (one), the updated value might get corrupted and cause an uninten-
tional interrupt to occur.
The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading
TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the
temporary storage register is read.
When Timer/Counter2 operates asynchronously, some considerations must be taken.
Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A
safe procedure for switching clock source is:
1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.
2. Select clock source by setting AS2 as appropriate.
3. Write new values to TCNT2, OCR2, and TCCR2.
4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and
5. Clear the Timer/Counter2 Interrupt Flags.
6. Enable interrupts, if needed.
The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external
clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU
main clock frequency must be more than four times the Oscillator frequency.
When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred
to a temporary register, and latched after two positive edges on TOSC1. The user
should not write a new value before the contents of the temporary register have been
transferred to its destination. Each of the three mentioned registers have their individual
temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2
write in progress. To detect that a transfer to the destination register has taken place,
the Asynchronous Status Register – ASSR has been implemented.
When entering Power-save or Extended Standby mode after having written to TCNT2,
OCR2, or TCCR2, the user must wait until the written register has been updated if
Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep
mode before the changes are effective. This is particularly important if the Output
Compare2 Interrupt is used to wake up the device, since the Output Compare function is
disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the
MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never
receive a compare match interrupt, and the MCU will not wake up.
If Timer/Counter2 is used to wake the device up from Power-save or Extended Standby
mode, precautions must be taken if the user wants to re-enter one of these modes: The
interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-
entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the
device will fail to wake up. If the user is in doubt whether the time before re-entering
Power-save or Extended Standby mode is sufficient, the following algorithm can be
used to ensure that one TOSC1 cycle has elapsed:
When the asynchronous operation is selected, the 32.768 kHZ Oscillator for
Timer/Counter2 is always running, except in Power-down and Standby modes. After a
TCR2UB.
1. Write a value to TCCR2, TCNT2 or OCR2.
2. Wait until the corresponding Update Busy Flag in ASSR returns to zero.
3. Enter Power-save or Extended Standby mode.
ATmega323(L)
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