atmega323l ATMEL Corporation, atmega323l Datasheet - Page 48

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atmega323l

Manufacturer Part Number
atmega323l
Description
Atmega323 8-bit Avr Microcontroller With 32k Bytes Of In-system Programmable Flash
Manufacturer
ATMEL Corporation
Datasheet
48
ATmega323(L)
• Bit 3 – CTC0/CTC2: Clear Timer/Counter on Compare Match
When the CTC0 or CTC2 control bit is set (one), Timer/Counter0 or Timer/Counter2 is
reset to $00 in the CPU clock cycle following a Compare Match. If the control bit is
cleared, the Timer/Counter continues counting and is unaffected by a Compare Match.
When a prescaling of 1 is used, and the Compare Register is set to C, the timer will
count as follows if CTC0/CTC2 is set:
... | C-1 | C | 0 | 1 | ...
When the prescaler is set to divide by 8, the timer will count like this:
... | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, C, C, C, C, C, C, C | 0, 0, 0, 0, 0, 0, 0, 0 |
1, 1, 1, ...
In PWM mode, this bit has a different function. If the CTC0 or CTC2 bit is cleared in
PWM mode, the Timer/Counter acts as an up/down counter. If the CTC0 or CTC2 bit is
set (one), the Timer/Counter wraps when it reaches $FF. Refer to page 49 for a detailed
description.
• Bits 2, 1, 0 – CS02, CS01, CS00/ CS22, CS21, CS20: Clock Select bits 2, 1, and 0
The Clock Select bits 2, 1, and 0 define the prescaling source of Timer/Counter0 and
Timer/Counter2.
Table 13. Clock 0 Prescale Select
Table 14. Clock 2 Prescale Select
CS02
CS22
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CS01
CS21
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CS00
CS20
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Stop, the Timer/Counter0 is Stopped
CK
CK/8
CK/64
CK/256
CK/1024
External Pin PB0(T0), Falling Edge
External Pin PB0(T0), Rising Edge
Description
Stop, the Timer/Counter2 is Stopped
PCK2
PCK2/8
PCK2 /32
PCK2/64
PCK2/128
PCK2/256
PCK2/1024
1457G–AVR–09/03

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