atmega323l ATMEL Corporation, atmega323l Datasheet - Page 72

• Manufacturer Part Number: atmega323l
• Description: Atmega323 8-bit Avr Microcontroller With 32k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

The SPI Status Register –
SPSR
72
ATmega323(L)
• Bit 5 – DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared
(zero). If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-
enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is
low when idle. Refer to Figure 43 and Figure 44 for additional information.
• Bit 2 – CPHA: Clock Phase
Refer to Figure 43 and Figure 44 for the functionality of this bit.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency f
Table 27. Relationship Between SCK and the Oscillator Frequency
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is gener-
ated if SPIE in SPCR is set (one) and global interrupts are enabled. If SS is an input and
is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is
cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set
(one), then accessing the SPI Data Register (SPDR).
Bit
$0E ($2E)
Read/Write
Initial Value
SPI2X
0
0
0
0
1
1
1
1
SPIF
R
7
0
ck
is shown in Table 27.
WCOL
R
6
0
SPR1
0
0
1
1
0
0
1
1
R
5
–
0
R
4
–
0
SPR0
0
1
0
1
0
1
0
1
3
R
0
–
R
2
–
0
SCK Frequency
R
1
–
0
f
f
f
f
ck
f
ck
f
ck
ck
f
f
ck
ck
ck
ck
/
/
/
128
/
/
/
/
/
SPI2X
16
64
32
64
4
2
8
R/W
1457G–AVR–09/03
0
0
SPSR