atmega323l ATMEL Corporation, atmega323l Datasheet - Page 40

• Manufacturer Part Number: atmega323l
• Description: Atmega323 8-bit Avr Microcontroller With 32k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Power-down Mode
Power-save Mode
Standby Mode
Extended Standby Mode
40
ATmega323(L)
When the SM2..0 bits are 010, the SLEEP instruction makes the MCU enter Power-
down mode. In this mode, the external Oscillator is stopped, while the external inter-
rupts, the Two-wire Serial Interface address watch, and the Watchdog continue
operating (if enabled). Only an External Reset, a Watchdog Reset, an Two-wire Serial
Interface address match interrupt, an external level interrupt on INT0 or INT1, or an
external edge interrupt on INT2 can wake up the MCU.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. This makes the MCU
less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator
clock, and if the input has the required level during this time, the MCU will wake up. The
period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25 C. The frequency of
the Watchdog Oscillator is voltage dependent as shown in the Electrical Characteristics
section.
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake-up period is defined by the same CKSEL
Fuses that define the Reset Time-out Period, as seen in Table 6 on page 27.
When the SM2..0 bits are 011, the SLEEP instruction forces the MCU into the Power-
save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set,
Timer/Counter2 will run during sleep. The device can wake up from either Timer Over-
f lo w o r Ou tp ut Co mp are e vent f r om Ti m er/ Cou nt er2 i f t he correspo ndi ng
Timer/Counter2 interrupt enable bits are set in TIMSK, and the Global Interrupt Enable
bit in SREG is set.
If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recom-
mended instead of Power-save mode because the contents of the registers in the
asynchronous timer should be considered undefined after wake-up in Power-save mode
if AS2 is 0.
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,
the SLEEP instruction forces the MCU into the Standby mode. This mode is identical to
Power-down with the exception that the Oscillator is kept running. From Standby mode,
the device wakes up in only six clock cycles.
When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected,
the SLEEP instruction forces the MCU into the Extended Standby mode. This mode is
identical to Power-save mode with the exception that the Oscillator is kept running.
From Extended Standby mode, the device wakes up in only six clock cycles.
1457G–AVR–09/03