atmega323l ATMEL Corporation, atmega323l Datasheet - Page 147

• Manufacturer Part Number: atmega323l
• Description: Atmega323 8-bit Avr Microcontroller With 32k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Alternate Functions of Port C
1457G–AVR–09/03
PORTCn has to be cleared (zero), the pin has to be configured as an output pin, or the
PUD bit has to be set. The Port C pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Table 52. DDCn Effects on Port C Pins
Note:
If the JTAG Interface is enabled, the pull-up resistors on pins PC5 (TDI), PC3 (TMS) and
PC2 (TCK) will be activated even if a reset occurs.
• TOSC2 – Port C, Bit 7
TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asyn-
chronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, and
becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator
is connected to this pin, and the pin can not be used as an I/O pin.
• TOSC1 – Port C, Bit 6
TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asyn-
chronous clocking of Timer/Counter1, pin PC6 is disconnected from the port, and
becomes the input of the inverting Oscillator amplifier. In this mode, a crystal Oscillator
is connected to this pin, and the pin can not be used as an I/O pin.
• TDI – Port C, Bit 5
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or
Data Register (scan chains). When the JTAG interface is enabled, this pin can not be
used as an I/O pin. Refer to the section “JTAG Interface and the On-chip Debug Sys-
tem” on page 157 for details on operation of the JTAG interface.
• TDO – Port C, Bit 4
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Regis-
ter. When the JTAG interface is enabled, this pin can not be used as an I/O pin. Refer to
the section “JTAG Interface and the On-chip Debug System” on page 157 for details on
operation of the JTAG interface.
• TMS – Port C, Bit 3
TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller
state machine. When the JTAG interface is enabled, this pin can not be used as an I/O
pin. Refer to the section “JTAG Interface and the On-chip Debug System” on page 157
for details on operation of the JTAG interface.
DDCn
0
0
0
1
1
1. n: 7…0, pin number
PORTCn
0
1
1
0
1
(in SFIOR)
PUD
X
X
X
0
1
Output
Output
Input
Input
Input
I/O
(1)
Pull-up
Yes
No
No
No
No
Comments
Tri-state (Hi-Z)
PCn will Source Current if Ext. Pulled
Low.
Tri-state (Hi-Z)
Push-pull Zero Output
Push-pull One Output
ATmega323(L)
147