mt90226ag ETC-unknow, mt90226ag Datasheet - Page 10

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

10
Pin Diagram - MT90225
The MT90225 uses a 384 pin PBGA with a 1.0mm ball pitch.
AA
AB
AC
AD
AE
AF
C
D
G
H
M
N
R
U
W
A
B
E
F
J
K
L
P
T
V
Y
RXSYN
RXSYN
RXSYN
RXSYN
RXSYN
TXCKio
TXCKio
TXCKio
DSTi[5]
DSTi[6]
RXCKi
TXSyn
cio[13]
TXSyn
cio[11]
TXSyn
VDD5 DSTi[7] RXCKi
VDD5
Ci[12]
Ci[13]
Ci[15]
VDD5
Ci[11]
DSTo
DSTo
DSTo
cio[6]
Ci[6]
DSTi
DSTi
[14]
[15]
[15]
[14]
26
NC
NC
26
[8]
[9]
[8]
[7]
[6]
DSTi[4] RXCKi
RXSYN
DSTi[8] RXCKi
RXSYN
TXCKio
TXCKio
TXCKio
RXCKi
RXCKi
RXCKi
RXCKi
RXCKi
TXSyn
cio[15]
TXSyn
cio[14]
TXSyn
cio[12]
Ci[14]
VDD5
DSTo
DSTo
VDD5
VDD5
VSS
Ci[5]
VSS
[10]
[12]
[15]
[12]
[10]
NC
NC
[11]
NC
25
[9]
[9]
[7]
[6]
25
RXSYN
RXSYN
RXSYN
TXCKio
TXCKio
TXCKio
RXCKi
RXCKi
TXSyn
TXSyn
TXSyn
Ci[10]
DSTo
DSTo
cio[9]
cio[8]
cio[7]
DSTo
Ci[4]
Ci[9]
DSTi
DSTi
DSTi
VSS
VSS
[11]
[12]
[13]
[14]
[15]
[13]
[12]
[11]
[10]
24
NC
NC
NC
NC
24
[3]
[5]
[6]
[7]
[5]
DSTi[3] RXCKi
RXSYN
RXSYN
DSTi[9]
TXCKio
RXCKi
RXCKi
TXSyn
cio[10]
VDD5 DSTi[2] RXSYN
DSTo
DSTo
DSTo
DSTi
VSS
V3.3
Ci[7]
Ci[8]
V3.3
V2.5
V3.3
V2.5
V3.3
VSS
VSS
[10]
[13]
[14]
[13]
NC
[11]
NC
NC
NC
23
[4]
[8]
23
RXSYN
TXCKio
Ci[3]
V3.3
V3.3
22
NC
NC
22
[2]
[5]
DSTi[1] DSTi[0]
RXSYN
TXCKio
RXCKi
TXSyn
DSTo
cio[5]
Ci[1]
Ci[2]
NC
21
[1]
[4]
[4]
21
RXSYN
TXCKio
RXCKi
TXSyn
VDD5
cio[4]
DSTo
Ci[0]
20
NC
20
[0]
[3]
[3]
TXCKio
TXSyn
Latch
VDD5
DSTo
Test2
cio[3]
NC
NC
Clk
19
[2]
[2]
19
Figure 3 - MT90225 Pinout (Bottom View)
TXCKio
TXSyn
TXSyn
DSTo
cio[2]
cio[1]
18
NC
NC
NC
NC
18
[1]
[1]
TXCKio
DSTo
V2.5
V3.3
NC
NC
NC
NC
17
[0]
[0]
17
TXSyn
VDD5
cio[0]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16
NC
NC
NC
16
Zarlink Semiconductor Inc.
VDD5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
15
15
V3.3
V2.5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
14
NC
NC
NC
14
or up_rd
up_oe
VDD5
up_cs
V2.5
VSS
VSS
VSS
VSS
VSS
VSS
V3.3
VSS
NC
NC
13
13
up_r/w
VDD5 up_a[6] up_a[3] up_a[0]
up_wr
up_a
up_a
VSS
VSS
VSS
VSS
VSS
VSS
[10]
[11]
12
NC
NC
NC
NC
12
or
up_a[7]
up_a[8] up_a[4] up_a[1]
up_a[9] up_a[5] up_a[2] VDD5
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
11
11
V3.3
V2.5
10
NC
NC
NC
10
up_irq
NC
PD
PD
PD
9
9
VDD5
up_d
up_d
[14]
[15]
PD
PD
PD
NC
8
8
Test3
up_d
up_d
up_d
up_d
TCK
[10]
[12]
[13]
PD
PD
[11]
7
7
up_d[8] up_d[5] up_d[2]
up_d[9] up_d[7]
VDD5 up_d[6] up_d[4] up_d[1]
TDO
V3.3
V3.3
TDI
NC
6
6
TRST
VDD5
TMS
VSS
VSS
5
5
REFCK
Data[0]
Data[9]
UTxClk
Addr[2]
Addr[4]
ata[10]
ata[14]
ata[13]
Reset
URxD
URxD
URxA
ddr[2]
UTxD
Test4
V3.3
SOC
V2.5
V3.3
V2.5
V3.3
V3.3
VSS
VSS
URx
UTx
UTx
UTx
UTx
VSS
NC
NC
[2]
4
4
Data Sheet
UTxPar UTxD
REFCK
REFCK
up_d[3] up_d[0]
Data[1]
Data[5]
Data[7]
ata[11]
ata[15]
Data[2]
Data[6]
ata[10]
Addr[3]
URxD
URxD
URxA
ddr[1]
VDD5
UTxD
VDD5
VDD5
URx-
VSS
URx
URx
URx
URx
Clav
CLK
VSS
UTx
UTx
UTx
Enb
UTx
NC
NC
NC
[0]
[3]
3
3
Data[0]
Data[3]
Data[8]
Data[1]
Data[3]
Addr[1]
REF[1]
ata[12]
ata[12]
ata[15]
VDD5
URxD
URxA
VDD5
VDD5
ddr[3]
UTxD
ata[8]
UTxD
VSS
Clav
VSS
URx
URx
URx
URx
URx
Enb
UTx
UTx
UTx
UTx
PLL
NC
Par
NC
NC
NC
NC
2
2
REFCK
Data[2]
Data[4]
Data[6]
Data[9]
ata[13]
Data[4]
Data[5]
ata[11]
ata[14]
Addr[0]
REF[0]
URxD
VDD5
VDD5
URxA
ddr[0]
URxA
ddr[4]
UTxD
ata[7]
UTxD
UTxD
Test1
SOC
URx
URx
URx
URx
UTx
UTx
UTx
UTx
PLL
NC
NC
NC
Clk
NC
[1]
1
1
AA
AB
AC
AD
AE
AF
M
W
A
B
C
D
E
F
G
H
K
N
P
R
T
U
V
Y
J
L