mt90226ag ETC-unknow, mt90226ag Datasheet - Page 67

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
8.0
8.1
Many off-the-shelf T1/E1/J1 framers require the generation of a 1.544 MHz or 2.048 MHz transmit clock reference
signal at an input pin. The MT9042 can generate both of these clocks and the ST-BUS back-plane signals (C4,F0).
Figure 15 provides an example implementation using existing T1/E1/J1 framers and a common 2 Mbps ST-BUS
backplane.
New generation Zarlink framers only require the ST-BUS 4.096 MHz (C4) clock and a Frame Pulse (F0i) at the
transmit interface. An internal PLL generates the required 1.544 MHz or 2.048 MHz transmit clock.
Figure 16 provides an example implementation based on the Zarlink MT90225 and the Zarlink MT9076 framers.
Each link has independent clock in ST-BUS format.
Figure 17 and Figure 18 exemplify an ATM over T1/E1 implementation supporting the asynchronous link operation
mode where the TXCLK signal is provided by the T1/E1 interface. Each T1/E1 framer uses independent clock and
synchronization signals. The Tx and Rx clocks and frame pulses are fully independent.
ATM LAYER
UTOPIA
BUS
BUS
Figure 15 - MT90225 interfacing MT9076 ST-BUS mode with all links synchronous.
Application Notes
Connecting the MT90225/226 to Various T1/E1/J1 Framers
RXSYNC[0-15]
TXSYNC[0-15]
MT90225
RXCK[0-15]
TXCK[0-15]
DSTo[0:15]
DEVICE
DSTi[0:15]
Clock Recovery and Dejitter
Functions
4.096 MHz
8 kHz
MT9042
Data Lines
I/FCLOCKS
ST-BUS
Dejittered TX CLK to Framers
Zarlink Semiconductor Inc.
(1.544 or 2.048 MHz)
Back-Plane
(ST-BUS)
TDM
I/F DATA
I/F DATA
I/F DATA
ST-BUS
ST-BUS
ST-BUS
or 8 kHz References
Receive Clock
(1.544 or 2.048 MHz)
External Source
Framer/LIU
Framer/LIU
Framer/LIU
MT9076B
MT9076B
MT9076B
Zarlink
Zarlink
Zarlink
Legacy Trunks
at 1.5 or 2 Mbps
Legacy Trunks
at 1.5 or 2 Mbps
Legacy Trunks
at 1.5 or 2 Mbps
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