mt90226ag ETC-unknow, mt90226ag Datasheet - Page 62

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

62
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
15:0
6:5
4:3
7
2
1
0
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Link enable
When 0, the TX port is in high impedance mode
When 1, the TX port is active
Data rate:
11: 8.192 Mb/sec.
10: 4.096 Mb/sec.
01: 2.048 Mb/sec
00: 1.544 Mb/sec
Multiplex mode select:
00: no multiplexing,
01: multiplex on a per byte basis, 2 links to 1 link. Valid only for ST-BUS mode.
10: multiplex on a per byte basis, 4 links to 1 link. Valid only for ST-BUS mode.
Clock and sync format:
When 0, TDM is in Generic mode: clock is 1x data rate and sync is 1 bit long at beginning
of frame.
When 1, TDM is ST-BUS Format: clock 2x data rate and sync as per ST-BUS format
Clock polarity:
When 0, the data is output/sampled at the falling edge of TXCK
When 1, the data is output/sampled at the rising edge of TXCK
This bit is ignored in ST-BUS Format.
Sync polarity:
When 0, the sync pulse is active low
When 1, the sync pulse is active high.
This bit is ignored in ST-BUS Format.
Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not in
use, the DSTo pin is in High Z mode for the corresponding time slot.
This registers controls time slots 15:0.
0x0600 - 0x060F (16 reg)
1 reg. per TX link.
0000
0x0610 - 0x061F (16 reg)
Control time slot 15:0
0000
Table 33 - TDM TX Link Control Register (continued)
Table 34 - TDM TX Mapping (timeslots 15:0) Register
Zarlink Semiconductor Inc.
Description
Description
Data Sheet