mt90226ag ETC-unknow, mt90226ag Datasheet - Page 33

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
4.3.1
In this mode, two links of 2.048 Mb/s are multiplexed onto a single link of 4.096 Mb/s. The links that are paired are
pre-determined: link 0 is multiplexed with link 1, link 2 is multiplexed with link 3 and so on. When link 0 and link 1
are multiplexed, the pins associated with link 1 cannot be used and are tri-stated, however, bit 7 of its TDM TX(RX)
Link Control registers must be set. The two links operate using the Clock and SYNC signals of link 0. The same
logic applies for the other groups.
As an example of this grouped multiplexing, the MT90225/226 support eight high speed links on links 0, 2, 4, 6, 8
10, 12 and 14.
Unlike Single mode, the only clock format supported is ST-BUS mode. The data rate is 4.096 Mb/s. A clock of 8.192
MHz is used and the Frame pulse indicates the first bit of the first time slot of a frame of 64 time slots. The mapping
registers of the 2 physical links are merged by bit-to-bit interleaving to form a larger mapping register supporting up
to 64 time slots.
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings. Note that both links in a pair must have the same settings.
4.3.2
In this mode, four links of 2.048 Mb/s are multiplexed onto a single link of 8.192 Mb/s. The links that are combined
are pre-determined: links 0, 1, 2 and 3 are grouped and the multiplexed input/output is available on link 0. When link
0 is used, the pins associated with links 1, 2 and 3 cannot be used and are tri-stated, however, bit 7 of TDM TX(RX)
Link Control registers for those three links must be set. The four links operate using the Clock and SYNC signal of
link 0. The same logic applies for the other groups.
As an example of this grouped multiplexing, the MT90225/226 supports four high speed links on links 0, 4, 8 and 12.
Unlike Single mode, the only clock format supported is ST-BUS mode. The data rate is 8.192 Mb/s. A clock of 16.384
MHz is used and the Frame pulse indicates the first bit of the first time slot of a frame of 128 time slots. The mapping
registers of the 4 physical links are merged by bit-to-bit interleaving to form a larger mapping register supporting up
to 128 time slots.
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings. Note that all four links in a group must have the same settings.
Data rate (bits 6:5) = 10
Multiplex mode (bits 4:3) = 01
Clock and Sync format (bit 2) = 1
Enable (bit 7) = 1
Cell delineation mode (bit 10 of TDM RX Link Control only) = 0
TX clock direction (bit 9 of TDM TX Link Control only) = 1
Data rate (bits 6:5) = 11
Multiplex mode (bits 4:3) = 10
Clock and Sync format (bit 2) = 1
Enable (bit 7) = 1
Cell delineation mode (bit 10 of TDM RX Link Control only) = 0
TX clock direction (bit 9 of TDM TX Link Control only) = 1
Multiplex mode - 2 link multiplexing
Multiplex mode - 4 link multiplexing
Zarlink Semiconductor Inc.
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