mt90226ag ETC-unknow, mt90226ag Datasheet - Page 73

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
AC Electrical Characteristics - Utopia Interface Transmit Timing ( 50 MHz)
Multi-PHY operation with up to 4 input loads of 10pF each (40 pF total)
Note 1: Greater than 50MHz operation is possible with less than worst case duty cycle, jitter and rise/fall times such as 52MHz
operation with 45/55% (or better) duty cycle and 2.5% (or better) jitter.
Note 1: Greater than 50MHz operation is possible with less than worst case duty cycle, jitter and rise/fall times such as 52MHz
operation with 45/55% (or better) duty cycle and 2.5% (or better) jitter.
Note 2: URxPAR is not valid for cases where URxClk low pulse is shorter than 7.9 nsec.
AC Electrical Characteristics - UTOPIA Interface Receive Timing ( 50 MHz)
Multi-PHY operation with up to 4 input loads of 10pF each (40 pF total)
UTxClk
UTxData[15:0], UTxSOC,
UTxEnb, UTxAddr[4:0]
UTxClav[0]
URxClk
URxEnb, URxAddr[4:0]
URxData[15:0], URxSOC,
URxClav[0], URxPAR
Signal name
Signal name
2
A->P
A->P
A<-P
A->P
A->P
A<-P
DIR
DIR
Item
tT10
tT12
tT11
tOD
Item
tT10
tT12
tT2
tT3
tT4
tT5
tT6
tT8
tT9
tT11
tOD
tT2
tT3
tT4
tT5
tT6
tT8
tT9
f1
Zarlink Semiconductor Inc.
f1
TxClk frequency (nominal)
TxClk duty cycle
TxClk peak-to-peak jitter
TxClk rise/fall time
Input setup to TxClk
Input hold from TxClk
Output delay from TxClk
Output hold from TxClk
Signal going low impedance to TxClk
Signal going high impedance to TxCLK
Signal going low impedance from TxClk
Signal going high impedance from
TxClk
RxClk frequency (nominal)
RxClk duty cycle
RxClk peak-to-peak jitter
RxClk rise/fall time
Input setup to RxClk
Input hold from RxClk
Output delay from RxClk
Output hold from RxClk
Signal going low impedance to RxClk
Signal going high impedance to RxClk
Signal going low impedance from
RxClk
Signal going high impedance from
RxClk
Description
Description
1
40%
Min.
40%
4 ns
1 ns
1 ns
4 ns
0 ns
1 ns
1 ns
4 ns
1 ns
1 ns
4 ns
0 ns
1 ns
1 ns
Min
1
0
0
-
-
-
-
-
-
50 MHz
50 MHz
14 ns
14 ns
Max.
60%
Max
60%
2 ns
2 ns
5%
5%
-
-
-
-
-
-
-
-
-
-
-
-
-
-
73