mt90226ag ETC-unknow, mt90226ag Datasheet - Page 46

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

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6.2.3
The IRQ Link TC Overflow Status Registers (0x0410 - 0x041F) report the overflow condition from any of the
counters associated with the TX TDM link, the RX TDM link or the TX UTOPIA I/F. They also report the overflow
condition from the level of the UTOPIA RX FIFO. The 10 interrupt sources are organized as follows:
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6.3
6.3.1
Since the MT90225/226 and microprocessor operate from two different clock sources, access to a MT90225/226
register is asynchronous. Data is synchronized between the MT90225/226 and the microprocessor using either
direct or indirect (synchronized) methods of access.
The direct method is used during a read access whenever data does not change or data changes do not represent
any problem. There is no register that clears status bits upon a read access. A write action is always required to
clear a status bit.
The indirect method is identified with ’S’ (indirect and need to synchronize with a ready bit) whereas the direct access
is identified with a ’D’ in the register tables.
6.3.2
Direct access registers can be written or read directly by the microprocessor, without having to use other registers.
Upon a write access to the MT90225/226 internal registers, the data is stored in an internal latch and transferred to
the destination register within 2.5 system clock cycles (50 nsec at 50 MHz). No specific action is required if the
microprocessor provides at least 50 nsec (with Chip Select signal inactive) between 2 consecutive write accesses
or between a write and a read back of the same register. If the microprocessor is faster, then consecutive accesses
must be inhibited or wait state(s) introduced (this option is available on most MCUs).
6.3.3
Indirect access registers cannot be accessed directly by the microprocessor. The value is transferred back and forth
using registers which hold a copy of the information (data) and internal address of the register. This is required to
stabilize the read value. Accessing any of the 24 bit counters is an example of this type of access. A ready bit is
implemented in the Counter Transfer Command Register (0x040F) when the transfer is completed.
6.3.4
The status bits will remain set until cleared by a specific write action from the microprocessor. Status bits are cleared
by overwriting a zero to the corresponding position in the source register. Each input status register has a related
interrupt enable register. When enabled, setting a bit in the interrupt enable register causes an interrupt to occur in
the corresponding status register bit.
6.3.4.1
Some registers include a toggle bit. Toggle bits are used to indicate a write action to any internal register has taken
place. Typically, this bit is toggled 2.5 system clock cycles after performing the write action. To use the toggle bit, its
state (either 0 or 1) must be read (polled) and its state is changed (toggled) when a write command is completed.
This bit is particularly useful when the processor clock is much faster than the MT90225/226 system clock.
1 bit (12) for the RX UTOPIA FIFO overflow
4 bits (11:8) for the UTOPIA Input counters
2 bits (7,5) for the TX TDM Link counters
3 bits (3:1) for the RX TDM Link counters
IRQ Link TC Overflow Status Registers
Microprocessor Interface Block
Access to the Various Registers
Direct Access
Indirect Access
Clearing of Status Bits
Toggle Bit
Zarlink Semiconductor Inc.
Data Sheet