mt90226ag ETC-unknow, mt90226ag Datasheet - Page 43

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
6.0
6.1
The MT90225/226 includes 144 24-bit counters to provide statistical information on the device’s operation. All the
counters are cleared by a hardware reset. A maskable interrupt can be generated when the counter overflows.
Counters can also be latched to capture the state of all registers at once.
A predetermined value can also be loaded into a counter. This feature can be used to generate an interrupt after a
specified number of cells is processed. Counter values are incremented by 1 for every event occurrence and, when
the count reaches all 1’s, will overflow (to all 0’s).
6.1.1
There are four counters associated with the each of the 16 UTOPIA Inputs (from ATM layer to the MT90225/226)
for a total of 64 counters. These counters record the following information:
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6.1.2
There are two counters associated with the each of the sixteen transmit TDM links for a total of 32 Transmit
counters. These counters record the following information:
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6.1.3
There are three counters associated with each of the sixteen receive TDM links for a total of 48 receive counters.
These counters record the following information and are active as soon as the RX TDM port is enabled:
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6.1.4
Accessing (READ) counters is a three step operation. First, the desired counter must be selected by writing to the
Select Counter Register (0x0432). Second, the READ command (’0x00x101’) is written to the Counter Transfer
Command (0x040F) register. This command causes the current three byte count value to be copied from the
specified counter to the two 16 bit-wide Counter Byte 3 Register (0x0430) and Counter Bytes 2 and 1 Register
(0x0431) registers (note that this value is unchanged until another counter read command is issued). And third, the
Counter Byte 3 Register (0x0430) and Counter Bytes 2 and 1 Register (0x0431) registers are read to obtain
the three byte count value of the selected counter.
Pre-loading (WRITE) a counter is also a three step function. First, the three byte pre-load value is written to the two
16 bit-wide Counter Byte 3 Register (0x0430) and Counter Bytes 2 and 1 Register (0x0431) registers.
Second, the identification of the counter to be pre-loaded is written to the Select Counter Register (0x0432). And
third, the WRITE command (’0x00x001’) is written to the Counter Transfer Command (0x040F) register.
the total number of cells or the total number of user cells received at the UTOPIA Input I/F
the total number of Idle Cells received at the UTOPIA Input I/F, removed or not
the total number of Unassigned Cells received at the UTOPIA Input I/F, removed or not
the number of cells having a single or multiple bit error in the HEC, removed or not but not including the
cells where the HEC is corrected
the total number of cells sent through the TDM link
the total number of Idle cells or the total number of user cells sent through the TDM link
the total number of cells received through the TDM link.
the total number of Idle cells or the total number of user cells received through the TDM link
the total number of cells with wrong HEC, discarded or not, received through the TDM link but not including
the cells where the HEC is corrected
Support Blocks
Counter Block
UTOPIA Input I/F counters
Transmit TDM I/F Counters
Receive TDM I/F Counters
Access to the Counters
Zarlink Semiconductor Inc.
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