mt90226ag ETC-unknow, mt90226ag Datasheet - Page 9

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

Data Sheet
Pin Diagram - MT90226
The MT90226 uses a 384 pin PBGA with a 1.0mm ball pitch.
AA
AB
AC
AD
AE
AF
M
W
A
B
C
D
E
F
G
H
K
L
N
P
R
T
U
V
Y
J
DSTi[14
DSTo[6] TXCKio
RXSYN
DSTi[6]
RXSYN
TXCKio
TXCKio
TXSyn-
RXCKi
VDD5
VDD5
Ci[12]
VDD5 TXSyn-
cio[6]
Ci[6]
[14]
26
NC
NC
NC
NC
NC
NC
PD
PD
PD
NC
NC
NC
26
[8]
[8]
]
RXSYN
TXSyn-
DSTi[4]
DSTi[8]
DSTo[1
DSTo[1
RXCKi
RXCKi
cio[14]
cio[12]
Ci[14]
VDD5
VDD5 TXSyn-
VDD5
VSS
VSS
[10]
[12]
25
NC
NC
NC
NC
NC
NC
NC
PD
PD
PD
NC
25
[6]
2]
0]
RXSYN
RXSYN
DSTi[12
TXCKio
TXCKio
RXCKi
RXCKi
Ci[10]
cio[8]
Ci[4]
VSS
VSS
[14]
[12]
[10]
NC
NC
NC
NC
NC
NC
NC
NC
NC
PD
NC
PD
PD
NC
NC
NC
24
[6]
24
]
RXSYN
DSTi[10
DSTo[8]
DSTo[1
TXSyn-
RXCKi
cio[10]
VDD5 DSTi[2]
VSS
V3.3
Ci[8]
V3.3
V2.5
V3.3
V2.5
V3.3
VSS
VSS
NC
NC
NC
NC
NC
NC
PD
NC
NC
NC
23
[4]
23
4]
]
RXCKi
V3.3
V3.3
NC
NC
PD
NC
22
[2]
22
DSTo[4]
RXSYN
TXCKio
Ci[2]
NC
NC
NC
PD
NC
21
[4]
21
RXSYN
DSTi[0]
TXSyn-
RXCKi
VDD5
cio[4]
Ci[0]
NC
NC
PD
20
20
[0]
DSTo[2]
TXCKio
Latch-
VDD5
Test2
NC
NC
Clk
19
PD
19
[2]
Figure 2 - MT90226 Pinout (Bottom View)
TXSyn-
cio[2]
18
NC
NC
NC
NC
NC
PD
PD
18
DSTo[0] TXSyn-
TXCKio
V2.5
V3.3
NC
NC
NC
NC
17
[0]
17
VDD5
cio[0]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
16
16
Zarlink Semiconductor Inc.
VDD5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
15
15
V3.3
VSS
VSS
VSS
VSS
VSS
VSS
V2.5
VSS
VSS
VSS
NC
NC
NC
14
14
or up_rd
up_oe
VDD5
up_cs up_a[11
V2.5
VSS
VSS
VSS
VSS
VSS
VSS
V3.3
VSS
NC
NC
13
13
up_a[10
up_r/w
VDD5 up_a[6] up_a[3] up_a[0] up_d[14
up_wr
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
12
12
or
]
]
up_a[7]
up_a[8] up_a[4] up_a[1] up_d[15
up_a[9] up_a[5] up_a[2] VDD5 up_d[13
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
11
11
V3.3
V2.5
10
NC
NC
NC
10
up_irq
NC
PD
PD
PD
9
9
VDD5
PD
PD
PD
NC
8
8
]
]
up_d[10
up_d[11
up_d[12
Test3
TCK
PD
PD
7
7
]
]
]
]
up_d[8] up_d[5] up_d[2]
up_d[9] up_d[7]
VDD5 up_d[6] up_d[4] up_d[1]
TDO
V3.3
V3.3
NC
TDI
6
6
TRST
VDD5
TMS
VSS
VSS
5
5
Data[10
Data[14
Data[13
REFCK
Data[0]
Data[9]
UTxClk UTxEnb
URxA-
UTxA-
UTxA-
Reset
ddr[2]
ddr[2]
ddr[4]
Test4
VSS
V3.3
URx-
URx-
URx-
SOC
V2.5
UTx-
V3.3
V2.5
UTx-
UTx-
V3.3
V3.3
VSS
VSS
NC
NC
[2]
4
4
]
]
]
Data[11]
Data[15
URxClk URxEnb URxA-
Data[10
UTxPar
REFCK
REFCK
up_d[3] up_d[0]
Data[1]
Data[5]
Data[7]
Data[2]
Data[6]
URxA-
UTxA-
VDD5
VDD5
VDD5
URx-
URx-
ddr[1]
ddr[3]
URx-
URx-
URx-
URx-
UTx-
UTx-
UTx-
VSS
VSS
Clav
NC
NC
NC
[0]
[3]
3
3
]
]
Data[12
URxPar VDD5
Data[12
Data[15
Data[0]
Data[3]
Data[8]
Data[1]
Data[3]
Data[8]
REF[1]
URxA-
VDD5
VDD5
UTxA-
VDD5
ddr[3]
ddr[1]
URx-
URx-
URx-
URx-
UTx-
UTx-
UTx-
UTx-
UTx-
UTx-
PLL-
VSS
Clav
VSS
NC
NC
NC
NC
NC
2
2
]
]
]
Data[11]
Data[13
Data[14
Data[2]
Data[4]
Data[6]
Data[9]
Data[4]
Data[5]
Data[7]
REFCK
URxA-
REF[0]
VDD5
UTxA-
ddr[0]
ddr[4]
ddr[0]
Test1
URx-
URx-
URx-
URx-
URx-
UTx-
UTx-
UTx-
UTx-
UTx-
UTx-
SOC
PLL-
NC
NC
NC
Clk
NC
[1]
1
1
]
]
AA
AB
AC
AD
AE
AF
G
M
W
A
B
C
D
E
F
H
J
K
L
N
P
R
T
U
V
Y
9