mt90226ag ETC-unknow, mt90226ag Datasheet - Page 58

• Manufacturer Part Number: mt90226ag
• Description: 16/8 Port Tc Phy Device
• Manufacturer: ETC-unknow

58
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Synchronized access The value in this register is used for internal access to the counter when the
Reset Value (Hex):
15:13
Bit #
Bit #
15:8
7:0
12
10
11
9
8
7
6
5
4
3
2
1
0
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Unused. Read all 0’s.
This bit is set when the RX UTOPIA FIFO associated with a link overflows. This bit is
cleared by writing 0.
This bit is set when the UTOPIA Input counter for all cells associated with a link overflows.
This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for Idle Cells associated with a link
overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for Unassigned Cells associated with a link
overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for HEC Errored Cells associated with a
link overflows. This bit is cleared by writing 0.
This bit is set when the TX TDM Link counter for all cells associated with a link overflows.
This bit is cleared by writing 0.
This bit is set when the TX TDM Link counter for Idle Cells associated with a link
overflows. This bit is cleared by writing 0.
Reserved. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
This bit is set when the RX TDM Link counter for all cells associated with a link overflows.
This bit is cleared by writing 0.
This bit is set when the RX TDM Link counter for Idle Cells associated with a link
overflows. This bit is cleared by writing 0.
This bit is set when the RX TDM Link counter for HEC Errored Cells associated with a link
overflows. This bit is cleared by writing 0.
Reserved. Write 0 for normal operation.
Unused. Read all 0’s.
A read accesses the MSB (byte #3) of the Counter selected in the Select Counter
register.
A write will hold the value to be written to the selected counter.
register operation
0x0410 - 0x041F (16 reg)
1 register per link. The RxClk and TxClk signals must be active for correct
0000
0x0430 (1 reg)
0000
transfer command is issued
Table 24 - IRQ Link Overflow Status Registers
Table 25 - Counter Byte 3 Register
Zarlink Semiconductor Inc.
Description
Description
Data Sheet