mt90226ag ETC-unknow, mt90226ag Datasheet - Page 79

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mt90226ag

Manufacturer Part Number
mt90226ag
Description
16/8 Port Tc Phy Device
Manufacturer
ETC-unknow
Datasheet
Data Sheet
Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle
1
2
3
4
5
UP_AD[11:0]
UP_D[15:0]
UP_R/W set-up time to UP_CS falling
edge
Address and Data set up before
rising edge of UP_CS
UP_AD and Data hold time after
UP_CS rising edge
UP_R/W low after rising edge or
UP_CS
UP_CS high before next UP_CS low
UP_R/W
UP_OE
UP_CS
Characteristics
t
ws
Figure 24 - CPU Interface Motorola Timing - Write Access
Zarlink Semiconductor Inc.
Sym
t
t
t
t
t
ADH
CSH
WS
WH
SU
(see Note 1)
Address Valid
Data Valid
Min
10
t
1
4
1
2
su
Typ
t
wh
Max
t
adh
t
system
csh
Units
cycle
clock
ns
ns
ns
ns
Test Conditions
79

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