FW82801E Intel, FW82801E Datasheet - Page 32

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

Intel
32
Table 6.
®
82801E C-ICH
82801E C-ICH Signal Description (Sheet 8 of 11)
/SWDMARDY#)
SRDMARDY#)
/(SDWSTB/
/(SDSTOP)
SDDACK#
SDD[15:0]
/(SDRSTB
SDDREQ
SDA[2:0]
SDCS1#
SDCS3#
SDIOW#
SDIOR#
SERIRQ
SIORDY
SERR#
Signal
Type
I/O
I/O
O
O
O
O
O
O
I
I
I
Secondary IDE Device Address: These output signals are connected to the
corresponding signals on the secondary IDE connectors. They are used to
indicate which byte in either the ATA command block or control block is being
addressed.
Secondary IDE Device Chip Selects for 100 Range: This signal is for the
ATA command register block. This output signal is connected to the
corresponding signal on the secondary IDE connector.
Secondary IDE Device Chip Select for 300 Range: This signal is for the
ATA control register block. This output signal is connected to the
corresponding signal on the secondary IDE connector.
Secondary IDE Device Data: These signals directly drive the corresponding
signals on the secondary IDE connector. There is a weak internal pull-down
resistor on SDD[7].
Secondary IDE Device DMA Acknowledge: This signal directly drives the
DAK# signal on the secondary IDE connectors. This signal is asserted by the
82801E C-ICH to indicate to the IDE DMA slave device that a given data
transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle.
This signal is used in conjunction with the PCI bus master IDE function and is
not associated with any AT-compatible DMA channel.
Secondary IDE Device DMA Request: This input signal is directly driven
from the DRQ signals on the secondary IDE connector. It is asserted by the
IDE device to request a data transfer, and used in conjunction with the PCI
bus master IDE function. It is not associated with any AT-compatible DMA
channel. There is a weak internal pull-down resistor on SDDREQ.
Secondary Disk I/O Read (PIO and Non-Ultra DMA): This is the command
to the IDE device that it may drive data on the SDD lines. Data is latched by
the 82801E C-ICH on the deassertion edge of SDIOR#. The IDE device is
selected either by the ATA register file chip selects (SDCS1# or SDCS3#) and
the SDA lines, or the IDE DMA acknowledge (SDDAK#).
Secondary Disk Write Strobe (Ultra DMA Writes to Disk): This is the data
write strobe for writes to disk. When writing to disk, the 82801E C-ICH drives
valid data on rising and falling edges of SDWSTB.
Secondary Disk DMA Ready (Ultra DMA Reads from Disk): This is the
DMA ready for reads from disk. When reading from disk, the 82801E C-ICH
deasserts SRDMARDY# to pause burst data transfers.
Secondary Disk I/O Write (PIO and Non-Ultra DMA): This is the command
to the IDE device that it may latch data from the SDD lines. Data is latched by
the IDE device on the deassertion edge of SDIOW#. The IDE device is
selected either by the ATA register file chip selects (SDCS1# or SDCS3#) and
the SDA lines, or the IDE DMA acknowledge (SDDAK#).
Secondary Disk Stop (Ultra DMA): The 82801E C-ICH asserts SDSTOP to
terminate a burst.
Serial Interrupt Request: This pin implements the serial interrupt protocol.
System Error: SERR# can be pulsed active by any PCI device that detects a
system error condition. Upon sampling SERR# active, the 82801E C-ICH has
the ability to generate an NMI, SMI#, or interrupt.
Secondary I/O Channel Ready (PIO): This signal keeps the strobe active
(SDIOR# on reads, SDIOW# on writes) longer than the minimum width. It
adds wait states to SIO transfers.
Secondary Disk Read Strobe (Ultra DMA Reads from Disk): When reading
from disk, the 82801E C-ICH latches data from the disk on rising and falling
edges of SDRSTB.
Secondary Disk DMA Ready (Ultra DMA Writes to Disk): When writing to
disk, SWDMARDY# is deasserted by the disk to pause burst data transfers.
Description
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