FW82801E Intel, FW82801E Datasheet - Page 70

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FW82801E

Manufacturer Part Number
FW82801E
Description
Communications I/O Controller Hub
Manufacturer
Intel
Datasheet

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4.5
70
Table 55. Power Sequencing and Reset Signal Timings
Figure 9. Clock Timing
Figure 10. Valid Delay From Rising Clock Edge
®
82801E C-ICH
Timing Diagrams
NOTES:
1. The V5Ref supply must power up before or simultaneous with its associated 3.3 V supply, and must power
2. The associated 3.3 V and 1.8 V supplies are assumed to power up or down together. The difference
3. The Vcc supplies must never be active while the VccRTC supply is inactive.
Sym
t170
t171
t172
t173
t174
t175
down simultaneous with or after the 3.3V supply. See Section 3.3.4 for details.
between the levels of the 3.3 V and 1.8 V supplies must never be greater than 2.0V.
VccRTC active to RTCRST# inactive
VccRTC supply active to Vcc supplies active
V5Ref active to Vcc3_3, Vcc1_8 active
Vcc supplies active to PWROK, VRMPWRGD
active
AC_RST# active low pulse width
AC_RST# inactive to BIT_CLK startup delay
Output
Clock
0.8V
Parameter
2.0V
High Time
Fall Time
1.5V
Valid Delay
Period
Low Time
VT
162.8
Min
10
5
0
0
1
Advance Information Datasheet
Max
-
-
-
-
Rise Time
Units
ms
ms
ms
ms
µs
ns
Notes
1, 2
3
2
26, 27
26, 27
Fig
26
26

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