FW82801E Intel, FW82801E Datasheet - Page 55

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

3.4.5
Advance Information Datasheet
Table 32. Power Plane and States for Output and I/O Signals (Sheet 3 of 3)
Power Planes for Input Signals
Table 33 shows the power plane associated with each input signal, as well as what device drives the
signal at various times. Valid states include:
NOTES:
1. The 82801E C-ICH sets these signals at reset for processor frequency strap.
2. I GPIO[18] will toggle at a frequency of approximately 1 Hz when the 82801E C-ICH comes out of reset
3. CPUPWRGD is an open-drain output that represents a logical AND of the VRMPWRGD and PWROK
4. GPIO[24:25, 27:28]: These signals remain tri-stated for up to 110 ms after RSMRST# deassertion. At this
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•
•
•
•
signals and, thus, are driven low by 82801E C-ICH when either VRMPWRGD or PWROK are inactive.
During boot, or during a hard reset with power cycling, CPUPWRGD will be expected to transition from low
to High-Z.
point, they will be driven to their default (High) state.
High
Low
Static: Will be high or low, but will not change
Driven: Will be high or low, and is allowed to change
Running: For input clocks
SMBCLK, SMBDATA
Signal Name
SMLINK[1:0]
GPIO[19:20]
GPIO[27:28]
STPCLK#
GPIO[18]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
SUSCLK
SPKR
Power Plane
Main I/O
Main I/O
Main I/O
CPU I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
Main I/O
System Management Interface
Unmuxed GPIO Signals
Miscellaneous Signals
SMBus Interface
Reset Signal
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
PCIRST#
PCIRST#
PCIRST#
PCIRST#
PCIRST#
PCIRST#
PCIRST#
internal pull-up
During Reset
High-Z with
HIgh-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High
High
High
High
Low
Intel
Running
®
82801E C-ICH
Immediately
after Reset
See Note 2
High-Z
High-Z
High-Z
High
High
High
High
High
High
Low
Low
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