FW82801E Intel, FW82801E Datasheet - Page 4

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

Contents
5.0
Figures
4
1
2
3
4
5
6
7
8
9
10 Valid Delay From Rising Clock Edge.......................................................................................... 70
11 Setup And Hold Times................................................................................................................ 71
12 Float Delay ................................................................................................................................. 71
13 Pulse Width ................................................................................................................................ 71
14 Output Enable Delay .................................................................................................................. 71
15 IDE PIO Mode ............................................................................................................................ 72
16 IDE Multiword DMA .................................................................................................................... 72
17 Ultra ATA Mode (Drive Initiating a Burst Read) .......................................................................... 73
18 Ultra ATA Mode (Sustained Burst) ............................................................................................. 73
19 Ultra ATA Mode (Pausing a DMA Burst) .................................................................................... 74
20 Ultra ATA Mode (Terminating a DMA Burst) .............................................................................. 74
21 USB Rise and Fall Times ........................................................................................................... 74
22 USB Jitter ................................................................................................................................... 75
23 USB EOP Width ......................................................................................................................... 75
24 SMBus Transaction .................................................................................................................... 75
25 SMBus Time-out ......................................................................................................................... 75
26 Power Sequencing and Reset Signal Timings ........................................................................... 76
27 1.8 V/3.3 V Power Sequencing................................................................................................... 76
28 C0 to C2 to C0 Timings .............................................................................................................. 76
29 Test Mode Entry (XOR Chain Example)..................................................................................... 77
30 Example XOR Chain Circuitry .................................................................................................... 78
4.2
4.3
4.4
4.5
Testability..................................................................................................................................... 77
5.1
5.2
5.3
System Configuration ................................................................................................................... 7
Intel
Ball Diagram (Top View)............................................................................................................. 11
Intel
Intel
Intel
Required External RTC Circuit ................................................................................................... 50
Example V5REF Sequencing Circuit .......................................................................................... 51
Clock Timing ............................................................................................................................... 70
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Functional Operating Range............................................................................................... 57
DC Characteristics.............................................................................................................. 58
AC Characteristics .............................................................................................................. 62
Timing Diagrams................................................................................................................. 70
Test Mode Description........................................................................................................ 77
Tri-state Mode..................................................................................................................... 78
XOR Chain Mode................................................................................................................ 78
5.3.1
82801E C-ICH Simplified Block Diagram ........................................................................... 8
82801E C-ICH Package (Top View) ................................................................................. 23
82801E C-ICH Package (Side View) ................................................................................ 24
82801E C-ICH Package (Bottom View)............................................................................ 24
XOR Chain Testability Algorithm Example ............................................................ 84
5.3.1.1
Test Pattern Consideration for XOR Chain 4......................................... 84
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