FW82801E Intel, FW82801E Datasheet - Page 30

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

Intel
30
Table 6.
®
82801E C-ICH
82801E C-ICH Signal Description (Sheet 6 of 11)
/PWDMARDY#)
/PRDMARDY#)
PIRQ[A:D]#
/(PDSTOP)
PDDACK#
/(PDWSTB
PDD[15:0]
/(PDRSTB
PDDREQ
PDCS3#
PDIOW#
PDIOR#
PIORDY
PERR#
Signal
Type
I/OD
I/O
I/O
O
O
O
O
I
I
Primary IDE Device Chip Select for 300 Range: This signal is for the ATA
control register block. This output signal is connected to the corresponding
signal on the primary IDE connector.
Primary IDE Device Data: These signals directly drive the corresponding
signals on the primary IDE connector. There is a weak internal pull-down
resistor on PDD[7].
Primary IDE Device DMA Acknowledge: This signal directly drives the
DAK# signal on the primary IDE connector. This signal is asserted by the
82801E C-ICH to indicate to the IDE DMA slave device that a given data
transfer cycle (assertion of DIOR# or DIOW#) is a DMA data transfer cycle.
This signal is used in conjunction with the PCI bus master IDE function and is
not associated with any AT-compatible DMA channel.
Primary IDE Device DMA Request: This input signal is directly driven from
the DRQ signal on the primary IDE connector. It is asserted by the IDE device
to request a data transfer, and used in conjunction with the PCI bus master
IDE function. This signal is not associated with any AT-compatible DMA
channel. There is a weak internal pull-down resistor on PDDREQ.
Primary Disk I/O Read (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may drive data on the PDD lines. Data is latched by the
82801E C-ICH on the deassertion edge of PDIOR#. The IDE device is
selected either by the ATA register file chip selects (PDCS1#, PDCS3#) and
the PDA lines, or the IDE DMA acknowledge (PDDAK#).
Primary Disk Write Strobe (Ultra DMA Writes to Disk): PDWSTB is the
data write strobe for writes to disk. When writing to disk, the 82801E C-ICH
drives valid data on rising and falling edges of PDWSTB.
Primary Disk DMA Ready (Ultra DMA Reads from Disk): PRDMARDY# is
the DMA ready for reads from disk. When reading from disk, the 82801E
C-ICH deasserts PRDMARDY# to pause burst data transfers.
Primary Disk I/O Write (PIO and Non-Ultra DMA): This is the command to
the IDE device that it may latch data from the PDD lines. Data is latched by
the IDE device on the deassertion edge of PDIOW#. The IDE device is
selected either by the ATA register file chip selects (PDCS1#, PDCS3#) and
the PDA lines, or the IDE DMA acknowledge (PDDAK#).
Primary Disk Stop (Ultra DMA): 82801E C-ICH asserts PDSTOP to
terminate a burst.
Parity Error: An external PCI device drives PERR# when it receives data that
has a parity error. The 82801E C-ICH drives PERR# when it detects a parity
error. The ICH can either generate an NMI# or SMI# upon detecting a parity
error (either detected internally or reported via the PERR# signal).
Primary I/O Channel Ready (PIO): This signal keeps the strobe active
(PDIOR# on reads, PDIOW# on writes) longer than the minimum width. It
adds wait states to PIO transfers.
Primary Disk Read Strobe (Ultra DMA Reads from Disk): When reading
from disk, the 82801E C-ICH latches data from the disk on rising and falling
edges of PDRSTB.
Primary Disk DMA Ready (Ultra DMA Writes to Disk): When writing to disk,
PWDMARDY# is deasserted by the disk to pause burst data transfers.
PCI Interrupt Requests: In Non-APIC Mode the PIRQx# signals can be
routed to interrupts 3:7, 9:12, 14, or 15 as described in the Interrupt Steering
section. Each PIRQx# line has a separate Route Control Register.
In APIC mode, these signals are connected to the internal I/O APIC in the
following fashion: PIRQ[A]# is connected to IRQ16, PIRQ[B]# to IRQ17,
PIRQ[C]# to IRQ18, and PIRQ[D]# to IRQ19. This frees the ISA interrupts.
Description
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