FW82801E Intel, FW82801E Datasheet - Page 25

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

3.0
3.1
Advance Information Datasheet
Table 6.
Signal Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional
groups according to their associated interface.
The “#” symbol at the end of the signal name indicates that the active, or asserted state occurs when
the signal is at a low voltage level. When “#” is not present, the signal is asserted when at the high
voltage level.
The following notations are used to describe the signal type:
I
O
OD
I/O
Alphabetical Signal Reference
82801E C-ICH Signal Description (Sheet 1 of 11)
APICD[1:0]
A20GATE
APICCLK
AD[31:0]
A20M#
Signal
Type
I/OD
I/O
O
I
I
Input pin
Output pin
Open drain output pin.
Bidirectional input/output pin.
A20 Gate: This signal is from the keyboard controller. It acts as an alternative
method to force the A20M# signal active. A20GATE eliminates the need for
the external OR gate needed with various other PCIsets.
Mask A20: A20M# goes active based on setting the appropriate bit in the
Port 92h register, or based on the A20GATE signal.
Speed Strap: During the reset sequence, 82801E C-ICH drives A20M# high
if the corresponding bit is set in the FREQ_STRP register.
PCI Address/Data: AD[31:0] is a multiplexed address and data bus. During
the first clock of a transaction, AD[31:0] contain a physical address (32 bits).
During subsequent clocks, AD[31:0] contain data. The 82801E C-ICH drives
all 0s on AD[31:0] during the address phase of all PCI Special Cycles.
APIC Clock: The APIC clock runs at 33.333 MHz.
APIC Data: These bidirectional open drain signals are used to send and
receive data over the APIC bus. As inputs, the data is valid on the rising edge
of APICCLK. As outputs, new data is driven from the rising edge of the
APICCLK.
Description
Intel
®
82801E C-ICH
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