FW82801E Intel, FW82801E Datasheet - Page 64

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

Intel
64
Table 44. PCI Interface Timing (Sheet 2 of 2)
Table 45. IDE PIO & Multiword DMA Mode Timing (Sheet 1 of 2)
®
82801E C-ICH
NOTES:
Sym
1. IORDY is internally synchronized. This timing is to guarantee recognition on the next clock.
2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2-5 PCI
3. PIORDY sample point from DIOx# assertion, PDIOx# active pulse width and PDIOx# inactive pulse width
4. PDIOx# inactive pulse width is programmable from 1-4 PCI clocks when the drive mode is Mode 2 or
t60
t61
t62
t63
t64
t65
t66
t67
t68
t69
t70
t71
t72
t73
Sym
t45
t46
t47
t48
t49
t50
clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register
cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE
timing register.
greater. Refer to the RCT field in the IDE Timing Register.
PDIOR#/PDIOW#/SDIOR#/SDIOW# Active From
CLK66 Rising
PDIOR#/PDIOW#/SDIOR#/SDIOW# Inactive From
CLK66 Rising
PDA[2:0]/SDA[2:0] Valid Delay From CLK66 Rising
PDCS1#/SDCS1#, PDCS3#/SDCS3# Active From
CLK66 Rising
PDCS1#/SDCS1#, PDCS3#/SDCS3# Inactive From
CLK66 Rising
PDDACK#/SDDACK# Active From CLK66 Rising
PDDACK#/SDDACK# Inactive From CLK66 Rising
PDDREQ/SDDREQ Setup Time to CLK66 Rising
PDDREQ/SDDREQ Hold From CLK66 Rising
PDD[15:0]/SDD[15:0] Valid Delay From CLK66
Rising
PDD[15:0]/SDD[15:0] Setup Time to CLK66 Rising
PDD[15:0]/SDD[15:0] Hold From CLK66 Rising
PIORDY/SIORDY Setup Time to CLK66 Rising
PIORDY/SIORDY Hold From CLK66 Rising
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
PERR#, PLOCK#, DEVSEL#, GNT[A:B]# Float
Delay from PCICLK Rising
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
SERR#, PERR#, DEVSEL#, Setup Time to
PCICLK Rising
C/BE[3:0]#, FRAME#, TRDY#, IRDY#, STOP#,
SERR#, PERR#, DEVSEL#, REQ[A:B]# Hold
Time from PCLKIN Rising
PCIRST# Low Pulse Width
GNT[A:B}#, GNT[5, 3:0]# Valid Delay from
PCICLK Rising
REQ[A:B]#, REQ[5, 3:0]# Setup Timer to PCICLK
Rising
Parameter
Parameter
Min
10
Min
2
2
2
2
2
2
2
7
7
2
7
7
7
12
2
7
0
1
2
Advance Information Datasheet
Max
Max
20
20
30
30
30
20
20
30
28
12
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
Notes
Notes
1
1
Figure
15, 16
15, 16
15, 16
15, 16
15, 16
15
15
15
16
16
16
15
15
Figure
12
11
11
13