FW82801E Intel, FW82801E Datasheet - Page 29

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

Advance Information Datasheet
Table 6.
82801E C-ICH Signal Description (Sheet 5 of 11)
LAN0_RXD[2:0]
LAN1_RXD[2:0]
LAN0_TXD[2:0]
LAN1_TXD[2:0]
LDRQ[1:0]#
LFRAME#
NC[10:1]
OC[1:0]#
PCIRST#
PDA[2:0]
PDCS1#
/FWH[4]
PCICLK
Signal
PAR
NMI
Type
I/O
—
O
O
O
O
O
O
I
I
I
I
Received Data: The LAN Connect component uses these signals to transfer
data and control information to the integrated LAN Controller. These signals
have integrated weak pull-up resistors.
Transmit Data: The integrated LAN Controller uses these signals to transfer
data and control information to the LAN Connect component.
LPC Serial DMA/Master Request Inputs: These signals are used to request
DMA or bus master access. Typically, they are connected to external Super
I/O device. An internal pull-up resistor is provided on these signals.
LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
No Connect. Do not connect these pins.
Optional: NC[10:6, 3:1] can be routed to a test point for use in manufacturing
NAND tree testing.
Non-Maskable Interrupt: NMI is used to force a non-maskable interrupt to
the processor. The 82801E C-ICH can generate an NMI when either SERR#
or IOCHK# is asserted. The processor detects an NMI when it detects a rising
edge on NMI. NMI is reset by setting the corresponding NMI source
enable/disable bit in the NMI Status and Control Register.
Speed Strap: During the reset sequence, 82801E C-ICH drives NMI high if
the corresponding bit is set in the FREQ_STRP register.
Overcurrent Indicators: These signals set corresponding bits in the USB
controllers to indicate that an overcurrent condition has occurred.
Calculated/Checked Parity: PAR uses “even” parity calculated on 36 bits,
AD[31:0] plus C/BE[3:0]#. “Even” parity means that the 82801E C-ICH counts
the number of 1s within the 36 bits plus PAR and the sum is always even. The
82801E C-ICH always calculates PAR on 36 bits, regardless of the valid byte
enables. The 82801E C-ICH generates PAR for address and data phases and
only guarantees PAR to be valid one PCI clock after the corresponding
address or data phase. The 82801E C-ICH drives and tri-states PAR
identically to the AD[31:0] lines except that the 82801E C-ICH delays PAR by
exactly one PCI clock. PAR is an output during the address phase (delayed
one clock) for all 82801E C-ICH initiated transactions. PAR is an output
during the data phase (delayed one clock) when the 82801E C-ICH is the
Initiator of a PCI write transaction, and when it is the target of a read
transaction. 82801E C-ICH checks parity when it is the target of a PCI write
transaction. If a parity error is detected, the 82801E C-ICH sets the
appropriate internal status bits, and has the option to generate an NMI# or
SMI#.
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all
transactions on the PCI Bus.
PCI Reset: 82801E C-ICH asserts PCIRST# to reset devices that reside on
the PCI bus. The 82801E C-ICH asserts PCIRST# during power-up and when
S/W initiates a hard reset sequence through the RC (CF9h) register. The
82801E C-ICH drives PCIRST# inactive a minimum of 1 ms after PWROK is
driven active. The 82801E C-ICH drives PCIRST# active a minimum of 1 ms
when initiated through the RC register.
Primary IDE Device Address: These output signals are connected to the
corresponding signals on the primary IDE connector. They are used to
indicate which byte in either the ATA command block or control block is being
addressed.
Primary IDE Device Chip Selects for 100 Range: This signal is for the ATA
command register block. This output signal is connected to the corresponding
signal on the primary IDE connector.
Description
Intel
®
82801E C-ICH
29