FW82801E Intel, FW82801E Datasheet - Page 34

• Manufacturer Part Number: FW82801E
• Description: Communications I/O Controller Hub
• Manufacturer: Intel

Intel
34
Table 6.
®
82801E C-ICH
82801E C-ICH Signal Description (Sheet 10 of 11)
SMBALERT#
SMLINK[1:0]
SIU0_RTS#
SIU1_RTS#
SIU0_RXD
SIU1_RXD
SMBDATA
SIU0_TXD
SIU1_TXD
/GPIO[11]
STPCLK#
SMBCLK
SUSCLK
THRM#
STOP#
TP[3:0]
Signal
SPKR
SMI#
Type
I/OD
I/OD
I/OD
I/O
O
O
O
O
O
O
I
I
I
I
Request To Send for UART0 and UART1: When low these pins informs the
modem or data set that CICH UART 0, 1 are ready to establish a
communication link. The RTS#x(x=0,1) output signals can be set to an active
low by programming the RTSx (x-0,1) (bit1) of the Modem control register to a
logic ‘1’. A Reset operation sets this signal to its inactive state (logic ‘1’).
LOOP mode operation holds this signal in its inactive state.
Serial Input for UART0 and UART1: Serial data input from device pin to the
receive port.
Serial Output for UART0 and UART1: Serial data output to the
communication peripheral/modem or data set. Upon reset, the TXD pins will
be set to MARKING condition (logic ‘1’ state).
SMBus Alert: This signal is used to wake the system or generate an SMI#. If
not used for SMBALERT#, it can be used as a GPI.
SMBus Clock: External pull-up is required.
SMBus Data: External pull-up is required.
System Management Interrupt: SMI# is an active low output synchronous
to PCICLK. It is asserted by the 82801E C-ICH in response to one of many
enabled hardware or software events.
System Management Link: These signals are an SMBus link to an optional
external system management ASIC or LAN controller. External pull-ups are
required.
NOTE: SMLINK[0] corresponds to an SMBus Clock signal and SMLINK[1]
Speaker: The SPKR signal is the output of counter 2 and is internally ANDed
with Port 61h bit 1 to provide Speaker Data Enable. This signal drives an
external speaker driver device, which in turn drives the system speaker. Upon
PCIRST#, its output state is 1.
NOTE: SPKR is sampled at the rising edge of PWROK as a functional strap.
Stop: STOP# indicates that the 82801E C-ICH, as a Target, is requesting the
Initiator to stop the current transaction. STOP# causes the 82801E C-ICH, as
an Initiator, to stop the current transaction. STOP# is an output when the
82801E C-ICH is a target and an input when the 82801E C-ICH is an Initiator.
STOP# is tri-stated from the leading edge of PCIRST#. STOP# remains
tri-stated until driven by the 82801E C-ICH.
Stop Clock Request: STPCLK# is an active low output synchronous to
PCICLK. It is asserted by the 82801E C-ICH in response to one of many
hardware or software events. When the processor samples STPCLK#
asserted, it responds by stopping its internal clock.
Suspend Clock: This signal is an output of the RTC generator circuit and is
used by other chips for the refresh clock.
Thermal Alarm: THRM# is an active low signal generated by external
hardware to start the hardware clock throttling mode. This signal can also
generate an SMI# or an SCI.
Test Points:
TP0: This signal must have an external pull-up to Vcc3_3.
TP1: Route to a test point with option to jumper to Vcc1_8. Used for NAND
tree testing. Otherwise jumper to Vcc1_8.
TP2 and TP3: Route to a test point with option to jumper to V
NAND tree testing. Otherwise jumper to V
corresponds to an SMBus Data signal.
See “Functional Straps” on page 49 for more details.
Description
Advance Information Datasheet
SS
.
SS
. Used for