Z8S180 Zilog., Z8S180 Datasheet - Page 113

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

9 8
UM005001-ZMP0400
Bit
Position Bit/Field R/W
3
1
–
Z 8018x Fam il y
M PU Us e r M anual
2
SM1:0
MMOD
Table 12. Channel 0 Destination
DM1
0
0
1
1
W
R/W
DM0
0
1
0
1
Value
Memory/I/O
Memory
Memory
Memory
I/O
Description
Source Mode Channel — Specifies whether the source
for channel 0 transfers is memory, I/O, or memory
mapped I/O and the corresponding address modifier.
Reference Table 13.
DMA Memory Mode Channel 0 — When channel 0 is
configured for memory to/from memory transfers, the
external
timing. Instead, two automatic transfer timing modes are
selectable - BURST (MMOD is 1) and CYCLE STEAL
(MMOD is 0). For BURST memory to/from memory
transfers, the DMAC takes control of the bus
continuously until the DMA transfer completes (as shown
by the byte count register is 0). In CYCLE STEAL mode,
the CPU is given a cycle for each DMA byte transfer
cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the
DREQ
ignored.
0 input times the transfer and thus MMOD is
DREQ
0 input is not used to control the transfer
Address Increment/Decrement
+ 1
-1
fixed
fixed