Z8S180 Zilog., Z8S180 Datasheet - Page 23

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

8
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
D0–D7. Data Bus (Bidirectional, Active High, 3-state). D0-D7 constitute
an 8-bit bidirectional data bus, used for the transfer of information to and
from I/O and memory devices. The data bus enters the high impedance
state during RESET and external bus acknowledge cycles.
DCD0. Data Carrier Detect 0 (Input, Active Low). This input is a
programmable modem control signal for ASCI channel 0.
DREQ0, DREQ1. DMA Request 0 and 1 (Input, Active Low). DREQ is
used to request a DMA transfer from one of the on-chip DMA channels.
The DMA channels monitor these inputs to determine when an external
device is ready for a read or write operation. These inputs can be
programmed to be either level- or edge-sensed. DREQ0 is multiplexed
with CKA0.
E. Enable Clock (Output, Active High). Synchronous machine cycle clock
output during bus transactions.
EXTAL. External Clock/Crystal (Input, Active High). Crystal oscillator
connection. An external clock can be input to the Z8X180 on this pin
when a crystal is not used. This input is Schmitt-triggered.
HALT. Halt/Sleep Status (Output, Active Low). This output is asserted
after the CPU has executed either the HALT or SLP instruction, and is
waiting for either non-maskable or maskable interrupt before operation
can resume. HALT is also used with the M1 and ST signals to decode
status of the CPU machine cycle.
INT0. Maskable Interrupt Request 0 (Input, Active Low). This signal is
generated by external I/O devices. The CPU honors this request at the end
of the current instruction cycle as long as the NMI and BUSREQ signals
are inactive. The CPU acknowledges this interrupt request with an
interrupt acknowledge cycle. During this cycle, both the M1 and IORQ
signals become Active.
INT1, INT2. Maskable Interrupt Requests 1 and 2 (Inputs, Active Low).
This signal is generated by external I/O devices. The CPU honors these
requests at the end of the current instruction cycle as long as the NMI,