Z8S180 Zilog., Z8S180 Datasheet - Page 55

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

40
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
IDLE Mode
If the Global Interrupt Enable Flag IEF1 is set to 1, and if an interrupt
source is enabled in the ITC, asserting the corresponding interrupt input
causes the Z8S180/Z8L180-class processors to exit STANDBY mode.
The CPU performs an interrupt acknowledge sequence appropriate to the
input being asserted when clocking is resumed if:
•
•
If the Global Interrupt Enable Flag IEF1 is disabled (reset to 0) and if an
interrupt source is enabled in the ITC, asserting the corresponding
interrupt input still causes the Z8S180/Z8L180-class processors to exit
STANDBY mode. The CPU proceeds to fetch and execute instructions
that follow the SLEEP instruction when clocking resumes.
If the Extend Maskable Interrupt input is not active until clocking
resumes, the Z8S180/Z8L180-class processors do not exit STANDBY
mode. If the Non-Maskable Interrupt (NMI) is not active until clocking
resumes, the Z8S180/Z8L180-class processors still exits the STANDBY
mode even if the interrupt sources go away before the timer times out,
because NMI is edge-triggered. The condition is latched internally when
NMI is asserted Low.
IDLE mode is another power-down mode offered by the Z8S180/
Z8L180-class processors.
1. Set bits 6 and 3 to
2. Set the I/O STOP bit (bit 5 of ICR, I/O Address =
3. Execute the SLEEP instruction
When the part is in IDLE mode, the clock oscillator is kept oscillating, but
the clock to the rest of the internal circuit, including the CLKOUT, is
stopped completely. IDLE mode is exited in a similar way as STANDBY
mode, using RESET, BUS REQUEST or EXTERNAL INTERRUPTS,
The interrupt input follows the normal interrupt daisy-chain protocol
The interrupt source is active until the acknowledge cycle is complete
0
and
1
, respectively.
3FH
to 1.