Z8S180 Zilog., Z8S180 Datasheet - Page 134

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

ASCI Receive Data Register Ch. 0 (RDR0: 08H)
ASCI Receive Data Register Ch. 1 (RDR1: 09H)
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
7
7
ASCI Receive Shift Register 0,1(RSR0, 1)
This register receives data shifted in on the RXA pin. When full, data is
automatically transferred to the ASCI Receive Data Register (RDR) if it
is empty. If RSR is not empty when the next incoming data byte is shifted
in, an overrun error occurs. The RSR is not program-accessible.
ASCI Receive Data Register 0,1 (RDR0, 1: I/O Address =
When a complete incoming data byte is assembled in RSR, it is
automatically transferred to the RDR if RDR is empty. The next incoming
data byte can be shifted into RSR while RDR contains the previous
received data byte. Thus, the ASCI receiver on Z80180 is double-
buffered.
\
On the Z8S180 and Z8L180-class processors are quadruple buffered. The
ASCI Receive Data Register is a read-only register. However, if RDRF =
6
6
5
5
ASCI Receive Channel 0
ASCI Receive Channel 1
4
4
R/W
R/W
0
0
3
3
2
2
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
1
1
08H
0
0
,
09H
)
119