Z8S180 Zilog., Z8S180 Datasheet - Page 138

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

ASCI Status Register 1 (STAT1: 05H)
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
6
5
RDRF
OVRN
PE
RDRF
R
7
ASCI Control Register A0, 1 (CNTLA0, 1)
Each ASCI channel Control Register A configures the major operating modes
such as receiver/transmitter enable and disable, data format, and multiprocessor
communication mode.
0
R
R
R
OVRN
R
6
0
Value
PE
R
5
0
Description
Receive Data Register Full — RDRF is set to 1 when an
incoming data byte is loaded into RDR. Note that if a
framing or parity error occurs, RDRF is still set and the
receive data (which generated the error) is still loaded
into RDR. RDRF is cleared to 0 by reading RDR, when
the DCD0 input is High, in IOSTOP mode, and during
RESET.
Overrun Error — OVRN is set to 1 when RDR is full
and RSR becomes full. OVRN is cleared to 0 when the
EFR bit (Error Flag Reset) of CNTLA is written to 0,
when DCD0 is High, in IOSTOP mode, and during
RESET.
Parity Error — PE is set to 1 when a parity error is
detected on an incoming data byte and ASCI parity
detection is enabled (the MOD1 bit of CNTLA is set to
1). PE is cleared to 0 when the EFR bit (Error Flag Reset)
of CNTLA is written to 0, when DCD0 is High, in
IOSTOP mode, and during RESET.
FE
R
4
0
R/W
RIE
3
0
CTS1E
R/W
2
0
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
TDRE
R
1
0
R/W
TIE
0
0
123