Z8S180 Zilog., Z8S180 Datasheet - Page 154

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

The error flags (PE, FE, and OVRN bits) are also held at
DCD0 input goes Low, these bits do not resume normal operation until
the status register (STAT0, is read. This first read of (STAT0, while
enabling normal operation, still indicates the DCD0 input is High (DCD0
bit = 1) even though it has gone Low. Thus, the STAT0 register must be
read twice to ensure the DCD0 bit is reset to
RTS0: Request to Send 0 (Output)
RTS0 allows the ASCI to control (start/stop) another communication
devices transmission (for example, by connection to that device's CTS
input). RTS0 is essentially a 1-bit output port, having no side effects on
other ASCI registers or flags.
CTS1: Clear to Send 1 (Input)
Channel 1 CTS1 input is multiplexed with Clocked Serial Receive Data
(RXS). The CTS1 function is selected when the CTS1E bit in STAT1 is
set to
Modem control signal timing is depicted in Figure 53 and Figure 54.
Figure 53.
Status Register Read
1
. When enabled, the CTS1 operation is equivalent to CTS0,
DCD0 Flag
DCD0 Pin
DCD0 Timing Diagram
0
:
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
0
. Even after the
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