Z8S180 Zilog., Z8S180 Datasheet - Page 41

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

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UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
BUSREQ
BUSACK
RD, WR
A0
D0
MREQ
IORQ
When the bus is released, the address (A0–A19), data (D0–D7), and
control (MREQ, IORQ, RD, and WR) signals are placed in the high
impedance state.
Dynamic RAM refresh is not performed when the Z8X180 has released
the bus. The alternate bus master must provide dynamic memory
refreshing if the bus is released for long periods of time.
Figure 16 illustrates BUSREQ/BUSACK bus exchange during a memory
read cycle. Figure 17 illustrates bus exchange when the bus release is
requested during a Z8X180 CPU internal operation. BUSREQ is sampled
at the falling edge of the system clock prior to T3, T1 and Tx (BUS
RELEASE state). If BUSREQ is asserted Low at the falling edge of the
clock state prior to Tx, another Tx is executed.
Figure 16.
–
–
A19
Phi
D7
T1
Bus Exchange Timing During Memory Read
CPU memory read cycle
T2
TW
T3
TX
Bus release cycle
TX
T1
CPU cycle
T1