Z8S180 Zilog., Z8S180 Datasheet - Page 121

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

106
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
Figure 46.
To initiate memory to/from memory DMA transfer for channel 0, perform
the following operations.
1. Load the memory source and destination address into SAR0 and DAR0
2. Specify memory to/from memory mode and address increment/
3. Load the number of bytes to transfer in BCR0.
4. Specify burst or cycle steal mode in the MMOD bit of DCNTL.
5. Program DE0 =
decrement in the SM0 SM1, DM0 and DM1 bits of DMODE.
and the DMA operation starts one machine cycle later. If interrupt
occurs at the same time, the DIE0 bit must be set to
Address
MREQ
Data
WR
Phi
RD
DMA Timing Diagram-CYCLE STEAL Mode
DMA cycle
1
T1 T2
(with DWE0 =
CPU cycle DMA cycle (transfer 1 byte)
LD g,m
Op Code
address
m
T3
T1
Source
memory
address
T2
Read data
T3
0
in the same access) in DSTAT
T1 T2
Destination
memory
address
Write data,
T3
T1 T2
CPU cycle
LD g,m
operand
address
1
T3
m
.
T1 T2
DMA cycle