Z8S180 Zilog., Z8S180 Datasheet - Page 164

no-image

Z8S180

Manufacturer Part Number
Z8S180
Description
ENHANCED Z180 MICROPROCESSOR
Manufacturer
Zilog.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z8S18010FEC
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8S18010FEC00TR
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8S18010FEG
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8S18010FSC
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8S18010FSC00TR
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
Z8S18010FSCZ180
Manufacturer:
ZILOG
Quantity:
748
Part Number:
Z8S18010FSG
Manufacturer:
Zilog
Quantity:
426
Part Number:
Z8S18010PSG
Manufacturer:
Zilog
Quantity:
48
Part Number:
Z8S18010VEC
Manufacturer:
ZILOG
Quantity:
12 388
Part Number:
Z8S18010VSC
Manufacturer:
ZILOG
Quantity:
250
Bit
Position Bit/Field R/W
4
2
0
TE
SS2
0
CSI/O Transmit/Receive Data Register (TRDR: I/O
Address = 0BH).
TRDR is used for both CSI/O transmission and reception. Thus, the
system design must insure that the constraints of half-duplex operation
are met (Transmit and receive operation cannot occur simultaneously).
For example, if a CSI/O transmission is attempted while the CSI/O is
receiving data, the CSI/O does not work.
TRDR is not buffered. Attempting to perform a CSI/O transmit while the
previous transmit data is still being shifted out causes the shift data to be
immediately updated, thereby corrupting the transmit operation in
progress. Similarly, reading TRDR during a transmit or receive must be
avoided.
R/W
R/W
Value
Description
Transmit Enable — A CSI/O transmit operation is
started by setting TE to 1. When TE is set to 1, the data
clock is enabled. When in internal clock mode, the data
clock is output from the CKS pin. In external clock mode,
the clock is input on the CKS pin. In either case, data is
shifted out on the TXS pin synchronous with the (internal
or external) data clock. After transmitting 8 bits of data,
the CSI/O automatically clears TE to 0, EF is set to 1, and
an interrupt (if enabled by EIE = 1) is generated. TE and
RE are never both set to 1 at the same time. TE is cleared
to 0 during RESET and IOSTOP mode.
Speed Select — Selects the CSI/O transmit/receive clock
source and speed. SS2, SS I and SS0 are all set to 1 during
RESET. Table 22 shows CSI/O Baud Rate Selection.
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
149

Related parts for Z8S180