Z8S180 Zilog., Z8S180 Datasheet - Page 135

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

120
ASCI Status Register 0 (STAT0: 04H)
UM005001-ZMP0400
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
6
Z 8018x Fam il y
M PU Us e r M anual
RDRF
OVRN
RDRF
R
7
0
can be read.
ASCI Status Register 0, 1 (STAT0, 1)
Each channel status register allows interrogation of ASCI
communication, error and modem control signal status, and enabling or
disabling of ASCI interrupts.
0
, data can be written into the ASCII Receive Data Register, and the data
R
R
OVRN
R
6
0
Value
PE
R
5
0
Description
Receive Data Register Full — RDRF is set to 1 when an
incoming data byte is loaded into RDR. If a framing or
parity error occurs, RDRF remains set and the receive
data (which generated the error) is still loaded into RDR.
RDRF is cleared to 0 by reading RDR, when the DCD0
input is High, in IOSTOP mode, and during RESET.
Overrun Error — OVRN is set to 1 when RDR is full
and RSR becomes full. OVRN is cleared to 0 when the
EFR bit (Error Flag Reset) of CNTLA is written to 0,
when DCD0 is High, in IOSTOP mode, and during
RESET.
FE
R
4
0
R/W
RIE
3
0
DCD0
R
2
0
TDRE
R
1
0
R/W
TIE
0
0