Z8S180 Zilog., Z8S180 Datasheet - Page 129

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

114
UM005001-ZMP0400
Z 8018x Fam il y
M PU Us e r M anual
DMAC Internal Interrupts
Figure 50 illustrates the internal DMA interrupt request generation circuit.
Figure 50.
DE0 and DE1 are automatically cleared to
completion (byte count is
channel 1, respectively. They remain
and DE1 use level sense, an interrupt occurs if the CPU IEF1 flag is set to
1
further DMA interrupts (by programming the channel DIE bit is
enabling CPU interrupts (for example, IEF1 is set to
the DMAC address and count registers, the DIE bit can be set to
reenable the channel interrupt, and at the same time DMA can resume by
programming the channel DE bit =
DMAC and NMI
NMI, unlike all other interrupts, automatically disables DMAC operation
by clearing the DME bit of DSTAT. Thus, the NMI interrupt service
routine responds to time-critical events without delay due to DMAC bus
usage. Also, NMI can be effectively used as an external DMA abort input,
recognizing that both channels are suspended by the clearing of DME.
DIE0
DIE1
DE0
. Therefore, the DMA termination interrupt service routine disables
DE1
DMA Interrupt Request Generation
0
) of a DMA operation for channel 0 and
IEF1
1
.
0
until a
0
by the Z8X180 at the
1
is written. Because DE0:
DMA ch1 Interrupt
Request
DMA ch0 Interrupt
Request
1
). After reloading
0
1
) before
to