MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 13

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

Table 2:
NOTE:
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, or 2.5 clocks, as shown in Figure 6.
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 3
indicates the operating frequencies at which each CAS
latency setting can be used.
operation or incompatibility with future versions may
result.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
LENGTH
BURST
The READ latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
Reserved states should not be used, as unknown
2
4
8
1. Whenever a boundary of the block is reached
2. For a burst length of two, A1-Ai select the two-
3. For a burst length of four, A2-Ai select the four-
4. For a burst length of eight, A3-Ai select the eight-
A2
0
0
0
0
1
1
1
1
within a given sequence above, the following
access wraps within the block.
data-element block; A0 selects the first access
within the block.
data-element block; A0-A1 select the first access
within the block.
data-element block; A0-A2 select the first access
within the block.
STARTING
ADDRESS
COLUMN
A1
A1
Burst Definition
0
0
1
1
0
0
1
1
0
0
1
1
A0
A0
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
SEQUENTIAL
ORDER OF ACCESSES WITHIN A
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
TYPE=
0-1
1-0
BURST
INTERLEAVED
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
TYPE=
0-1
1-0
13
Table 3:
Operating Mode
MODE REGISTER SET command with bits A7-A13
each set to zero, and bits A0-A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9-A13 each set to
zero, bit A8 set to one, and bits A0-A6 set to the desired
values. Although not required by the Micron device,
JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL,
it should always be followed by a LOAD MODE REGIS-
TER command to select normal operating mode.
reserved for future use and/or test modes. Test modes
and reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
COMMAND
COMMAND
The normal operating mode is selected by issuing a
All other combinations of values for A7-A13 are
DQS
DQS
CK#
CK#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQ
DQ
SPEED
CK
CK
-75
Figure 6: CAS Latency
READ
READ
T0
Burst Length = 4 in the cases shown
Shown with nominal t AC and nominal t DQSCK
T0
CAS Latency (CL)
75 £ f £ 100
CL = 2
TRANSITIONING DATA
CLOCK FREQUENCY (MHZ)
CL = 2.5
NOP
NOP
ALLOWABLE OPERATING
T1
CL = 2
T1
1Gb: x4, x8, x16
DDR SDRAM
T2
NOP
NOP
T2
PRELIMINARY
©2003 Micron Technology. Inc.
T2n
T2n
75 £ f £ 133
CL = 2.5
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n