MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 57

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
39. The voltage levels used are derived from a mini-
-10
-20
-30
-40
-50
-60
-70
-80
80
70
60
50
40
30
20
10
0
Figure 36: Reduced Drive Pull-Down
0
0.0
0.0
Figure 37: Reduced Drive Pull-Up
e. The full variation in the ratio of the maximum
f. The full variation in the ratio of the nominal
mum V
practice, the voltage levels obtained from a
properly terminated bus will provide signifi-
cantly different voltage values.
to minimum pull-up and pull-down current
should be between 0.71 and 1.4 for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
DD
0.5
0.5
level and the referenced test load. In
Characteristics
Characteristics
1.0
1.0
V
DD
V
Q - V
OUT
OUT
(V)
(V)
1.5
1.5
2.
2.0
2.5
57
40. V
41. V
42. This maximum value is derived from the refer-
43. For slew rates of greater than 1V/ns the (LZ) tran-
44. During initialization, V
45. The current Micron part operates below the slow-
46. Not used.
47. Reserved for future use.
48. Random addressing changing 50 percent of data
49. Random addressing changing 100 percent of data
50. CKE must be active (HIGH) during the entire time
51. I
52. Whenever the operating frequency is altered, not
pulse width £ 3ns and the pulse width can not
be greater than 1/3 of the cycle rate. V
shoot: V
and the pulse width can not be greater than 1/3
of the cycle rate.
enced test load. In practice, the values obtained in
a typical terminated design may reflect up to
310ps less for
(MAX) will prevail over
(MAX) condition.
t
sition will start about 310ps earlier.
equal to or less than V
may be 1.35V maximum during power up, even if
V
series resistance is used between the V
and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
changing at every transfer.
changing at every transfer.
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
to a valid high or low logic level. I
to I
control inputs to remain stable. Although I
I
case.”
including jitter, the DLL is required to be reset fol-
lowed by 200 clock cycles before any Read com-
mand.
DQSCK (MIN) +
RFC has been satisfied.
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
IH
2N specifies the DQ, DQS and DM to be driven
2N, and I
DD
/V
overshoot: V
and V
2F except I
DD
IL
Q are 0V, provided a minimum of 42 W of
DD
(MIN) = -1.5V for a pulse width £ 3ns
Q must track each other.
DD
t
HZ (MAX) and the last DVW.
2Q are similar, I
t
DD
IH
RPRE (MAX) condition.
t
LZ (MIN) will prevail over
2Q specifies the address and
(MAX) = V
1Gb: x4, x8, x16
DD
DD
t
DQSCK (MAX) +
Q, V
+ 0.3V. Alternatively, V
DDR SDRAM
TT
PRELIMINARY
, and V
DD
©2003 Micron Technology. Inc.
DD
DD
Q + 1.5V for a
2F is “worst
2Q is similar
REF
IL
TT
must be
under-
supply
t
DD
RPST
t
HZ
2F,
TT