MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 35

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. DI b = data-in for column b, DO n = data-out for column n.
2. An interrupted burst of 4 is shown; one data element is written.
3.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. DQS is required at T1n, T2, and T2n (nominal case) to register DM.
6. If the burst of 8 was used, DM and DQS would be required at T3 - T3n because the READ command would not mask these data
t
elements.
WTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements).
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
Figure 25: WRITE to READ - Odd Number of Data, Interrupting
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
t
WTR
T2n
35
Bank a,
READ
Col n
T3
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T3n
CL = 2
CL = 2
CL = 2
T4
NOP
DON’T CARE
1Gb: x4, x8, x16
T5
NOP
DO
DO
DO
n
n
n
DDR SDRAM
TRANSITIONING DATA
T5n
PRELIMINARY
©2003 Micron Technology. Inc.
T6
NOP
T6n