MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 33

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MT46V128M8

Manufacturer Part Number
MT46V128M8
Description
DOUBLE DATA RATE (DDR) SDRAM
Manufacturer
MICRON [Micron Technology]
Datasheet

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NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. DI b = data-in for column b, DO n = data-out for column n.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4.
5. The READ and WRITE commands are to same device. However, the READ and WRITE commands may be to different devices, in
6. A10 is LOW with the WRITE command (auto precharge is disabled).
t
which case
WTR is referenced from the first positive CK edge after the last data-in pair.
COMMAND
ADDRESS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
t
WTR is not required and the READ command could be applied earlier.
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
Figure 23: WRITE to READ - Uninterrupting
DI
b
NOP
T1
DI
b
DI
b
T1n
NOP
T2
T2n
33
T3
NOP
t
WTR
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Bank a,
READ
Col n
T4
DON’T CARE
CL = 2
CL = 2
CL = 2
1Gb: x4, x8, x16
T5
NOP
DDR SDRAM
TRANSITIONING DATA
PRELIMINARY
©2003 Micron Technology. Inc.
T6
NOP
DO
DO
DO
n
n
n
T6n

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