MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 63

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. V
2. Reset the DLL with A8 = H while programming the operating parameters.
3.
4. The two AUTO REFRESH commands at Td0 and Te0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE com-
V
even if V
pin. Once initialized, V
t
be issued.
bank. If another LMR command is issued, the same operating parameter, previously issued, must be used.
mand, RA = Row Address, BA = Bank Address.
MRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can
SYMBOL
t
TT
DD
CK (2.5)
t
CK (2)
A11, A12, A13
t
t
t
t
is not applied directly to the device; however,
Q, V
COMMAND
IH
CH
CL
IS
F
F
BA0, BA1
A0-A9,
TT
DD
V
DQS
CK#
CKE
A10
V
V
DD
DM
V
DQ
, and V
CK
TT
REF
DD
6
Q
/V
1
DD
t
VTD
Q are 0V, provided a minimum of 42 ohms of series resistance is used between the V
REF
1
MIN
0.45
0.45
7.5
.90
.90
10
, must be equal to or less than V
REF
LVCMOS
LOW LEVEL
T = 200µs
Power-up: V
Figure 42: Initialize And Load Mode Registers
must always be powered with in specified range.
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DD
MAX
and CK stable
0.55
0.55
t IS
t
13
13
IS
T0
NOP
High-Z
High-Z
t IH
t
t
IH
CH
t
CK
t
CL
ALL BANKS
t IS
PRE
T1
t IH
UNITS
t
t
t
VTD should be greater than or equal to zero to avoid device latch-up.
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CK
CK
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Load Extended
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Mode Register
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+ 0.3V. Alternatively, V
t IS
t IS
t IS
BA0 = H,
BA1 = L
CODE
CODE
LMR
Ta0
t IH
t IH
t IH
t MRD
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Load Mode
Register
BA0 = L,
BA1 = L
CODE
CODE
LMR
Tb0
SYMBOL
t
t
MRD
t
t
VTD
t
t
RFC
2
IH
t MRD
IS
RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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ALL BANKS
t
IS
TT
Tc0
PRE
200 cycles of CK
t
IH
may be 1.35V maximum during power up,
t RP
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MIN
120
15
20
1
1
0
Td0
3
AR
t RFC
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1Gb: x4, x8, x16
TT
Te0
AR
MAX
supply and the input
DDR SDRAM
13
t RFC
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5
PRELIMINARY
©2003 Micron Technology. Inc.
ACT 5
Tf0
RA
RA
BA
DON’T CARE
UNITS
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