MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 40

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

Table 6:
Notes: 1-6
NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
1. CKE
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. CKE must not drop low during a column access. For a READ, this means CKE must stay high until after the Read Postamble time;
6. Upon exit of the Self Refresh mode the DLL is automatically enabled, but a DLL Reset must still occur. A minimum of 200 clock
CKE
for a WRITE, CKE must stay high until the WRITE Recovery Time (
cycles is needed before applying a READ command for the DLL to lock. DESELECT or NOP commands should be issued on any
clock edges occurring during the
H
H
L
L
n-1
n
COMMAND
is the logic state of CKE at clock edge n; CKE
CKE
CKE
CK#
H
H
L
L
n
CK
No READ/WRITE
access in progress
is the command registered at clock edge n, and ACTION
Truth Table – CKE
n
CURRENT STATE
Bank(s) Active
All Banks Idle
All Banks Idle
Power-Down
Power-Down
Self Refresh
Self Refresh
VALID
T0
t
XSNR period.
t
IS
NOP
T1
Enter power-down mode
See Table 7 on page 41
Figure 30: Power-Down
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
COMMAND
X
X
T2
n-1
(
(
(
(
)
(
)
)
)
)
was the state of CKE at the previous clock edge.
(
(
(
)
(
)
(
)
)
)
n
40
t
WR) has been met.
Ta0
n
ACTION
Maintain Power-Down
Maintain Self Refresh
Exit Power-Down
Exit Self Refresh
Precharge Power-Down Entry
Active Power-Down Entry
Self Refresh Entry
is a result of COMMAND
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
t
IS
Ta1
NOP
Exit power-down mode
n
1Gb: x4, x8, x16
.
Ta2
NOP
DON’T CARE
DDR SDRAM
PRELIMINARY
©2003 Micron Technology. Inc.
VALID
NOTES
6