MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 44

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTE:
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to
CL
BL = Bust Length
WRITEs with auto precharge disabled.
end the READ burst prior to asserting a WRITE command.
RU
= CAS Latency (CL) rounded up to the next integer
FROM COMMAND
WRITE w/AP
READ w/AP
b. The minimum delay from a read or write command with auto precharge enabled, to a com-
This device supports concurrent auto precharge such that when a read with auto pre-
charge is enabled or a write with auto precharge is enabled any command to other
banks is allowed, as long as that command does not interrupt the read or write data
transfer already in process. In either case, all other related limitations apply (e.g., con-
tention between read data and write data must be avoided).
mand to a different bank is summarized below.
WRITE or WRITE w/AP
WRITE or WRITE w/AP
READ or READ w/AP
READ or READ w/AP
TO COMMAND
PRECHARGE
PRECHARGE
ACTIVE
ACTIVE
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(WITH CONCURRENT AUTO PRECHARGE)
[1 + (BL/2)] *
MINIMUM DELAY
[CL
RU
(BL/2) *
(BL/2) *
+
1
1
1
1
(BL/2)] *
t
t
t
t
CK
CK
CK
CK
1Gb: x4, x8, x16
t
CK +
t
t
CK
CK
t
DDR SDRAM
CK
t
WTR
PRELIMINARY
©2003 Micron Technology. Inc.