MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 39

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

PRECHARGE
is used to deactivate the open row in a particular bank
or the open row in all banks. The bank(s) will be avail-
able for a subsequent row access some specified time
(
A10 determines whether one or all banks are to be pre-
charged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been pre-
charged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
t
RP) after the PRECHARGE command is issued. Input
The PRECHARGE command as shown in Figure 29,
Figure 29: PRECHARGE Command
A0–A9, A11, A12, A13
BA = Bank Address (if A10 is LOW;
otherwise “Don’t Care”)
BA0,1
CAS#
RAS#
WE#
A10
CKE
CK#
CS#
CK
HIGH
ALL BANKS
ONE BANK
DON’T CARE
BA
39
Power-down (CKE Not Active)
be active at all times an access is in progress, from the
issuing of a READ or WRITE command until comple-
tion of the access. Thus a clock suspend is not sup-
ported. For READs, an access completion is defined
when the Read Postamble is satisfied; for WRITEs, an
access completion is defined when the Write Recovery
time (
entered when CKE is registered LOW and all Table 6
(page 40)criteria are met. If power-down occurs when
all banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates
the input and output buffers, excluding CK, CK#, and
CKE. For maximum power savings, the DLL is frozen
during precharge power-down mode. Exiting power-
down requires the device to be at the same voltage and
frequency as when it entered power-down. However,
power-down duration is limited by the refresh require-
ments of the device (
signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are “Don’t Care.”
The power-down state is synchronously exited when
CKE is registered HIGH (in conjunction with a NOP or
DESELECT command). A valid executable command
may be applied one clock cycle later.
Unlike SDR SDRAMs, DDR SDRAMs require CKE to
Power-down as shown in Figure 30 on page 40, is
While in power-down, CKE LOW and a stable clock
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR) is satisfied.
t
REFC).
1Gb: x4, x8, x16
DDR SDRAM
PRELIMINARY
©2003 Micron Technology. Inc.