MT46V128M8 MICRON [Micron Technology], MT46V128M8 Datasheet - Page 18

• Manufacturer Part Number: MT46V128M8
• Description: DOUBLE DATA RATE (DDR) SDRAM
• Manufacturer: MICRON [Micron Technology]

Operations
Bank/Row Activation
issued to a bank within the DDR SDRAM, a row in that
bank must be “opened.” This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 8.
READ or WRITE command may be issued to that row,
subject to the
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock
edge after the ACTIVE command on which a READ or
WRITE command can be entered. For example, a
specification of 20ns with a 133 MHz clock (7.5ns
period) results in 2.7 clocks rounded to 3. This is
reflected in Figure 9, which covers any case where 2 <
t
case for
other specification limits from time units to clock
cycles).
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
RCD (MIN)/
RRD.
COMMAND
Before any READ or WRITE commands can be
After a row is opened with an ACTIVE command, a
A subsequent ACTIVE command to a different row
A subsequent ACTIVE command to another bank
Figure 9: Example: Meeting
BA0, BA1
A0-A13
CK#
CK
t
RCD; the same procedure is used to convert
t
CK £ 3. (Figure 9 also shows the same
t
RCD specification.
Bank x
Row
ACT
T0
NOP
T1
t
RCD (MIN) should
t
RRD
t
RC.
NOP
t
RCD (
T2
t
RCD
t
RRD) MIN When 2 <
Bank y
Row
ACT
18
T3
Figure 8: Activating a Specific Row in a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T4
NOP
BA0, BA1
t RCD
A0-A13
RAS#
CAS#
WE#
Specific Bank
CKE
CK#
CS#
CK
t
RCD (
T5
NOP
HIGH
RA = Row Address
BA = Bank Address
1Gb: x4, x8, x16
t
RRD) MIN/
RA
BA
DDR SDRAM
RD/WR
Bank y
T6
Col
PRELIMINARY
©2003 Micron Technology. Inc.
DON’T CARE
t
CK£3
T7
NOP